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https://github.com/antonblanchard/microwatt.git
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595a758400
This adds a pipelined 33-bit by 33-bit signed multiplier with one cycle latency to the execute pipeline, and uses it for the mullw, mulhw and mulhwu instructions. Because it has one cycle of latency we can assume that its result is available in the second execute stage without needing to add busy logic to the second stage. This adds both a generic version of the multiplier and a Xilinx-specific version using four DSP slices of the Artix-7. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
294 lines
8.0 KiB
VHDL
294 lines
8.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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library unisim;
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use unisim.vcomponents.all;
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-- Signed 33b x 33b multiplier giving 64-bit product, with no addend.
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entity multiply_32s is
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port (
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clk : in std_logic;
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stall : in std_ulogic;
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m_in : in MultiplyInputType;
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m_out : out MultiplyOutputType
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);
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end entity multiply_32s;
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architecture behaviour of multiply_32s is
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signal clocken : std_ulogic;
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signal data1 : std_ulogic_vector(52 downto 0);
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signal data2 : std_ulogic_vector(34 downto 0);
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signal m00_p, m01_p : std_ulogic_vector(47 downto 0);
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signal m00_pc : std_ulogic_vector(47 downto 0);
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signal m10_p, m11_p : std_ulogic_vector(47 downto 0);
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signal m10_pc : std_ulogic_vector(47 downto 0);
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signal p0_pat, p0_patb : std_ulogic;
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signal p1_pat, p1_patb : std_ulogic;
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signal product_lo : std_ulogic_vector(22 downto 0);
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begin
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-- sign extend
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data1 <= std_ulogic_vector(resize(signed(m_in.data1(32 downto 0)), 53));
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data2 <= std_ulogic_vector(resize(signed(m_in.data2(32 downto 0)), 35));
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clocken <= m_in.valid and not stall;
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m00: DSP48E1
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generic map (
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ACASCREG => 0,
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ALUMODEREG => 0,
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AREG => 0,
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BCASCREG => 0,
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BREG => 0,
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CARRYINREG => 0,
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CARRYINSELREG => 0,
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CREG => 0,
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INMODEREG => 0,
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MREG => 0,
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OPMODEREG => 0,
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PREG => 0
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)
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port map (
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A => "0000000" & data1(22 downto 0),
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ACIN => (others => '0'),
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ALUMODE => "0000",
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B => '0' & data2(16 downto 0),
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BCIN => (others => '0'),
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C => (others => '0'),
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CARRYCASCIN => '0',
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CARRYIN => '0',
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CARRYINSEL => "000",
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CEA1 => '0',
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CEA2 => '0',
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CEAD => '0',
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CEALUMODE => '0',
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CEB1 => '0',
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CEB2 => '0',
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CEC => '0',
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CECARRYIN => '0',
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CECTRL => '0',
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CED => '0',
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CEINMODE => '0',
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CEM => '0',
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CEP => '0',
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CLK => clk,
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D => (others => '0'),
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INMODE => "00000",
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MULTSIGNIN => '0',
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OPMODE => "0110101",
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P => m00_p,
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PCIN => (others => '0'),
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PCOUT => m00_pc,
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RSTA => '0',
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RSTALLCARRYIN => '0',
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RSTALUMODE => '0',
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RSTB => '0',
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RSTC => '0',
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RSTCTRL => '0',
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RSTD => '0',
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RSTINMODE => '0',
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RSTM => '0',
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RSTP => '0'
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);
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m01: DSP48E1
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generic map (
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ACASCREG => 0,
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ALUMODEREG => 0,
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AREG => 0,
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BCASCREG => 0,
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BREG => 0,
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CARRYINREG => 0,
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CARRYINSELREG => 0,
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CREG => 0,
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INMODEREG => 0,
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MREG => 0,
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OPMODEREG => 0,
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PREG => 0
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)
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port map (
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A => "0000000" & data1(22 downto 0),
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ACIN => (others => '0'),
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ALUMODE => "0000",
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B => data2(34 downto 17),
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BCIN => (others => '0'),
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C => (others => '0'),
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CARRYCASCIN => '0',
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CARRYIN => '0',
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CARRYINSEL => "000",
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CEA1 => '0',
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CEA2 => '0',
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CEAD => '0',
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CEALUMODE => '0',
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CEB1 => '0',
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CEB2 => '0',
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CEC => '0',
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CECARRYIN => '0',
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CECTRL => '0',
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CED => '0',
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CEINMODE => '0',
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CEM => '0',
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CEP => '0',
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CLK => clk,
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D => (others => '0'),
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INMODE => "00000",
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MULTSIGNIN => '0',
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OPMODE => "1010101",
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P => m01_p,
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PCIN => m00_pc,
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RSTA => '0',
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RSTALLCARRYIN => '0',
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RSTALUMODE => '0',
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RSTB => '0',
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RSTC => '0',
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RSTCTRL => '0',
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RSTD => '0',
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RSTINMODE => '0',
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RSTM => '0',
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RSTP => '0'
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);
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m10: DSP48E1
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generic map (
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ACASCREG => 0,
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ALUMODEREG => 0,
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AREG => 0,
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BCASCREG => 0,
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BREG => 0,
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CARRYINREG => 0,
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CARRYINSELREG => 0,
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CREG => 1,
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INMODEREG => 0,
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MASK => x"fffffffe00ff",
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OPMODEREG => 0,
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PREG => 0,
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USE_PATTERN_DETECT => "PATDET"
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)
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port map (
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A => data1(52 downto 23),
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ACIN => (others => '0'),
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ALUMODE => "0000",
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B => '0' & data2(16 downto 0),
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BCIN => (others => '0'),
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C => std_ulogic_vector(resize(signed(m01_p(38 downto 6)), 48)),
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CARRYCASCIN => '0',
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CARRYIN => '0',
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CARRYINSEL => "000",
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CEA1 => '0',
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CEA2 => '0',
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CEAD => '0',
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CEALUMODE => '0',
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CEB1 => '0',
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CEB2 => '0',
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CEC => clocken,
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CECARRYIN => '0',
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CECTRL => '0',
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CED => '0',
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CEINMODE => '0',
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CEM => clocken,
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CEP => '0',
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CLK => clk,
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D => (others => '0'),
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INMODE => "00000",
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MULTSIGNIN => '0',
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OPMODE => "0110101",
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P => m10_p,
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PATTERNDETECT => p0_pat,
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PATTERNBDETECT => p0_patb,
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PCIN => (others => '0'),
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PCOUT => m10_pc,
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RSTA => '0',
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RSTALLCARRYIN => '0',
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RSTALUMODE => '0',
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RSTB => '0',
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RSTC => '0',
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RSTCTRL => '0',
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RSTD => '0',
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RSTINMODE => '0',
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RSTM => '0',
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RSTP => '0'
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);
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m11: DSP48E1
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generic map (
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ACASCREG => 0,
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ALUMODEREG => 0,
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AREG => 0,
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BCASCREG => 0,
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BREG => 0,
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CARRYINREG => 0,
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CARRYINSELREG => 0,
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CREG => 0,
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INMODEREG => 0,
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MASK => x"fffffc000000",
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OPMODEREG => 0,
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PREG => 0,
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USE_PATTERN_DETECT => "PATDET"
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)
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port map (
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A => data1(52 downto 23),
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ACIN => (others => '0'),
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ALUMODE => "0000",
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B => data2(34 downto 17),
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BCIN => (others => '0'),
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C => (others => '0'),
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CARRYCASCIN => '0',
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CARRYIN => '0',
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CARRYINSEL => "000",
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CEA1 => '0',
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CEA2 => '0',
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CEAD => '0',
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CEALUMODE => '0',
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CEB1 => '0',
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CEB2 => '0',
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CEC => '0',
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CECARRYIN => '0',
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CECTRL => '0',
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CED => '0',
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CEINMODE => '0',
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CEM => clocken,
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CEP => '0',
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CLK => clk,
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D => (others => '0'),
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INMODE => "00000",
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MULTSIGNIN => '0',
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OPMODE => "1010101",
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P => m11_p,
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PATTERNDETECT => p1_pat,
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PATTERNBDETECT => p1_patb,
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PCIN => m10_pc,
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RSTA => '0',
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RSTALLCARRYIN => '0',
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RSTALUMODE => '0',
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RSTB => '0',
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RSTC => '0',
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RSTCTRL => '0',
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RSTD => '0',
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RSTINMODE => '0',
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RSTM => '0',
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RSTP => '0'
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);
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m_out.result(127 downto 64) <= (others => '0');
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m_out.result(63 downto 40) <= m11_p(23 downto 0);
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m_out.result(39 downto 23) <= m10_p(16 downto 0);
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m_out.result(22 downto 0) <= product_lo;
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m_out.overflow <= not ((p0_pat and p1_pat) or (p0_patb and p1_patb));
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process(clk)
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begin
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if rising_edge(clk) and stall = '0' then
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m_out.valid <= m_in.valid;
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product_lo <= m01_p(5 downto 0) & m00_p(16 downto 0);
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end if;
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end process;
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end architecture behaviour;
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