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https://github.com/antonblanchard/microwatt.git
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5e140298a5
The decode2 stage was spaghetti code and needed cleaning up. Create a series of functions to pull fields from a ppc instruction and also a series of helpers to extract values for the execution units. As suggested by Paul, we should pass all signals to the execution units and only set the valid signal conditionally, which should use less resources. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
197 lines
7.2 KiB
VHDL
197 lines
7.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.decode_types.all;
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package common is
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type ctrl_t is record
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lr: std_ulogic_vector(63 downto 0);
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ctr: std_ulogic_vector(63 downto 0);
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tb: std_ulogic_vector(63 downto 0);
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carry: std_ulogic;
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end record;
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type Fetch1ToFetch2Type is record
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valid: std_ulogic;
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nia: std_ulogic_vector(63 downto 0);
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end record;
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type Fetch2ToDecode1Type is record
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valid: std_ulogic;
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nia: std_ulogic_vector(63 downto 0);
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insn: std_ulogic_vector(31 downto 0);
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end record;
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constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', others => (others => '0'));
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type Decode1ToDecode2Type is record
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valid: std_ulogic;
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nia: std_ulogic_vector(63 downto 0);
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insn: std_ulogic_vector(31 downto 0);
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decode: decode_rom_t;
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end record;
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constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', decode => decode_rom_init, others => (others => '0'));
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type Decode2ToExecute1Type is record
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valid: std_ulogic;
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insn_type: insn_type_t;
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nia: std_ulogic_vector(63 downto 0);
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write_reg: std_ulogic_vector(4 downto 0);
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read_reg1: std_ulogic_vector(4 downto 0);
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read_reg2: std_ulogic_vector(4 downto 0);
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read_data1: std_ulogic_vector(63 downto 0);
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read_data2: std_ulogic_vector(63 downto 0);
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const1: std_ulogic_vector(7 downto 0);
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const2: std_ulogic_vector(5 downto 0);
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const3: std_ulogic_vector(4 downto 0);
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cr: std_ulogic_vector(31 downto 0);
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lr: std_ulogic;
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rc: std_ulogic;
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input_carry: std_ulogic;
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output_carry: std_ulogic;
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input_cr: std_ulogic;
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output_cr: std_ulogic;
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input_cr_data: std_ulogic_vector(31 downto 0);
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end record;
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constant Decode2ToExecute1Init : Decode2ToExecute1Type := (valid => '0', insn_type => OP_ILLEGAL, lr => '0', rc => '0', input_carry => '0', output_carry => '0', input_cr => '0', output_cr => '0', others => (others => '0'));
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type Decode2ToMultiplyType is record
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valid: std_ulogic;
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insn_type: insn_type_t;
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nia: std_ulogic_vector(63 downto 0);
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write_reg: std_ulogic_vector(4 downto 0);
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data1: std_ulogic_vector(64 downto 0);
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data2: std_ulogic_vector(64 downto 0);
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rc: std_ulogic;
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end record;
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constant Decode2ToMultiplyInit : Decode2ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL, rc => '0', others => (others => '0'));
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type Decode2ToRegisterFileType is record
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read1_reg : std_ulogic_vector(4 downto 0);
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read2_reg : std_ulogic_vector(4 downto 0);
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read3_reg : std_ulogic_vector(4 downto 0);
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end record;
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type RegisterFileToDecode2Type is record
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read1_data : std_ulogic_vector(63 downto 0);
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read2_data : std_ulogic_vector(63 downto 0);
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read3_data : std_ulogic_vector(63 downto 0);
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end record;
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type Decode2ToCrFileType is record
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read_cr_nr_1 : integer;
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read_cr_nr_2 : integer;
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end record;
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type CrFileToDecode2Type is record
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read_cr_data : std_ulogic_vector(31 downto 0);
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read_cr_data_1 : std_ulogic_vector(3 downto 0);
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read_cr_data_2 : std_ulogic_vector(3 downto 0);
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end record;
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type Execute1ToFetch1Type is record
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redirect: std_ulogic;
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redirect_nia: std_ulogic_vector(63 downto 0);
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end record;
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constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', others => (others => '0'));
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type Decode2ToLoadstore1Type is record
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valid : std_ulogic;
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nia: std_ulogic_vector(63 downto 0);
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load : std_ulogic; -- is this a load or store
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addr1 : std_ulogic_vector(63 downto 0);
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addr2 : std_ulogic_vector(63 downto 0);
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data : std_ulogic_vector(63 downto 0); -- data to write, unused for read
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write_reg : std_ulogic_vector(4 downto 0); -- read data goes to this register
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length : std_ulogic_vector(3 downto 0);
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byte_reverse : std_ulogic;
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sign_extend : std_ulogic; -- do we need to sign extend?
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update : std_ulogic; -- is this an update instruction?
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update_reg : std_ulogic_vector(4 downto 0); -- if so, the register to update
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end record;
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constant Decode2ToLoadstore1Init : Decode2ToLoadstore1Type := (valid => '0', load => '0', byte_reverse => '0', sign_extend => '0', update => '0', others => (others => '0'));
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type Loadstore1ToLoadstore2Type is record
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valid : std_ulogic;
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load : std_ulogic;
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addr : std_ulogic_vector(63 downto 0);
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data : std_ulogic_vector(63 downto 0);
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write_reg : std_ulogic_vector(4 downto 0);
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length : std_ulogic_vector(3 downto 0);
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byte_reverse : std_ulogic;
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sign_extend : std_ulogic;
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update : std_ulogic;
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update_reg : std_ulogic_vector(4 downto 0);
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end record;
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type Loadstore2ToWritebackType is record
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valid : std_ulogic;
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write_enable: std_ulogic;
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write_reg : std_ulogic_vector(4 downto 0);
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write_data : std_ulogic_vector(63 downto 0);
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write_enable2: std_ulogic;
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write_reg2 : std_ulogic_vector(4 downto 0);
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write_data2 : std_ulogic_vector(63 downto 0);
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end record;
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constant Loadstore2ToWritebackInit : Loadstore2ToWritebackType := (valid => '0', write_enable => '0', write_enable2 => '0', others => (others => '0'));
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type Execute1ToExecute2Type is record
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valid: std_ulogic;
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write_enable : std_ulogic;
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write_reg: std_ulogic_vector(4 downto 0);
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write_data: std_ulogic_vector(63 downto 0);
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write_cr_enable : std_ulogic;
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write_cr_mask : std_ulogic_vector(7 downto 0);
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write_cr_data : std_ulogic_vector(31 downto 0);
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rc : std_ulogic;
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end record;
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constant Execute1ToExecute2Init : Execute1ToExecute2Type := (valid => '0', write_enable => '0', write_cr_enable => '0', rc => '0', others => (others => '0'));
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type Execute2ToWritebackType is record
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valid: std_ulogic;
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write_enable : std_ulogic;
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write_reg: std_ulogic_vector(4 downto 0);
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write_data: std_ulogic_vector(63 downto 0);
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write_cr_enable : std_ulogic;
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write_cr_mask : std_ulogic_vector(7 downto 0);
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write_cr_data : std_ulogic_vector(31 downto 0);
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end record;
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constant Execute2ToWritebackInit : Execute2ToWritebackType := (valid => '0', write_enable => '0', write_cr_enable => '0', others => (others => '0'));
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type MultiplyToWritebackType is record
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valid: std_ulogic;
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write_reg_enable : std_ulogic;
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write_reg_nr: std_ulogic_vector(4 downto 0);
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write_reg_data: std_ulogic_vector(63 downto 0);
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write_cr_enable: std_ulogic;
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write_cr_mask: std_ulogic_vector(7 downto 0);
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write_cr_data: std_ulogic_vector(31 downto 0);
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end record;
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constant MultiplyToWritebackInit : MultiplyToWritebackType := (valid => '0', write_reg_enable => '0', write_cr_enable => '0', others => (others => '0'));
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type WritebackToRegisterFileType is record
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write_reg : std_ulogic_vector(4 downto 0);
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write_data : std_ulogic_vector(63 downto 0);
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write_enable : std_ulogic;
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write_reg2 : std_ulogic_vector(4 downto 0);
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write_data2 : std_ulogic_vector(63 downto 0);
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write_enable2 : std_ulogic;
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end record;
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constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_enable2 => '0', others => (others => '0'));
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type WritebackToCrFileType is record
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write_cr_enable : std_ulogic;
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write_cr_mask : std_ulogic_vector(7 downto 0);
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write_cr_data : std_ulogic_vector(31 downto 0);
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end record;
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constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', others => (others => '0'));
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-- Would prefer not to expose this outside the register file, but ghdl
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-- doesn't support external names
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type regfile is array(0 to 32) of std_ulogic_vector(63 downto 0);
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end common;
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package body common is
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end common;
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