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e41cb01bca
The ability to stop the core using the debug interface has been broken
since commit bb4332b7e6b5 ("Remove fetch2 pipeline stage"), which
removed a statement that cleared the valid bit on instructions when
their stop_mark was 1.
Fix this by clearing r.req coming out of fetch1 when r.stop_mark = 1.
This has the effect of making i_out.valid be 0 from the icache. We
also fix a bug in icache.vhdl where it was not honouring i_in.req when
use_previous = 1.
It turns out that the logic in fetch1.vhdl to handle stopping and
restarting was not correct, with the effect that stopping the core
would leave NIA pointing to the last instruction executed, not the
next instruction to be executed. In fact the state machine is
unnecessary and the whole thing can be simplified enormously - we
need to increment NIA whenever stop_in = 0 in the previous cycle.
Fixes: bb4332b7e6b5 ("Remove fetch2 pipeline stage")
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
126 lines
3.6 KiB
VHDL
126 lines
3.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity fetch1 is
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generic(
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RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0');
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ALT_RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0')
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);
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port(
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clk : in std_ulogic;
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rst : in std_ulogic;
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-- Control inputs:
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stall_in : in std_ulogic;
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flush_in : in std_ulogic;
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stop_in : in std_ulogic;
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alt_reset_in : in std_ulogic;
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-- redirect from execution unit
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e_in : in Execute1ToFetch1Type;
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-- redirect from decode1
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d_in : in Decode1ToFetch1Type;
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-- Request to icache
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i_out : out Fetch1ToIcacheType;
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-- outputs to logger
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log_out : out std_ulogic_vector(42 downto 0)
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);
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end entity fetch1;
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architecture behaviour of fetch1 is
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type reg_internal_t is record
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mode_32bit: std_ulogic;
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end record;
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signal r, r_next : Fetch1ToIcacheType;
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signal r_int, r_next_int : reg_internal_t;
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signal log_nia : std_ulogic_vector(42 downto 0);
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begin
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regs : process(clk)
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begin
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if rising_edge(clk) then
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log_nia <= r.nia(63) & r.nia(43 downto 2);
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if r /= r_next then
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report "fetch1 rst:" & std_ulogic'image(rst) &
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" IR:" & std_ulogic'image(r_next.virt_mode) &
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" P:" & std_ulogic'image(r_next.priv_mode) &
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" E:" & std_ulogic'image(r_next.big_endian) &
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" 32:" & std_ulogic'image(r_next_int.mode_32bit) &
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" R:" & std_ulogic'image(e_in.redirect) & std_ulogic'image(d_in.redirect) &
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" S:" & std_ulogic'image(stall_in) &
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" T:" & std_ulogic'image(stop_in) &
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" nia:" & to_hstring(r_next.nia) &
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" SM:" & std_ulogic'image(r_next.stop_mark);
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end if;
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r <= r_next;
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r_int <= r_next_int;
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end if;
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end process;
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log_out <= log_nia;
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comb : process(all)
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variable v : Fetch1ToIcacheType;
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variable v_int : reg_internal_t;
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begin
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v := r;
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v_int := r_int;
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v.sequential := '0';
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if rst = '1' then
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if alt_reset_in = '1' then
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v.nia := ALT_RESET_ADDRESS;
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else
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v.nia := RESET_ADDRESS;
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end if;
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v.virt_mode := '0';
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v.priv_mode := '1';
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v.big_endian := '0';
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v_int.mode_32bit := '0';
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elsif e_in.redirect = '1' then
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v.nia := e_in.redirect_nia(63 downto 2) & "00";
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if e_in.mode_32bit = '1' then
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v.nia(63 downto 32) := (others => '0');
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end if;
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v.virt_mode := e_in.virt_mode;
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v.priv_mode := e_in.priv_mode;
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v.big_endian := e_in.big_endian;
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v_int.mode_32bit := e_in.mode_32bit;
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elsif d_in.redirect = '1' then
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v.nia := d_in.redirect_nia(63 downto 2) & "00";
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if r_int.mode_32bit = '1' then
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v.nia(63 downto 32) := (others => '0');
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end if;
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elsif stall_in = '0' then
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-- If the last NIA value went down with a stop mark, it didn't get
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-- executed, and hence we shouldn't increment NIA.
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if r.stop_mark = '0' then
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if r_int.mode_32bit = '0' then
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v.nia := std_ulogic_vector(unsigned(r.nia) + 4);
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else
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v.nia := x"00000000" & std_ulogic_vector(unsigned(r.nia(31 downto 0)) + 4);
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end if;
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v.sequential := '1';
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end if;
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end if;
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v.req := not rst and not stop_in;
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v.stop_mark := stop_in;
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r_next <= v;
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r_next_int <= v_int;
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-- Update outputs to the icache
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i_out <= r;
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end process;
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end architecture behaviour;
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