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554b753172
This adds a local socket that can be used to communicate with the debug tool (which will be committed separately) and generates the JTAG signals. We generate the low level JTAG signals, thus directly driving the simulated BSCANE2, and the Xilinx DTM Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
106 lines
2.6 KiB
VHDL
106 lines
2.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.sim_jtag_socket.all;
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library unisim;
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use unisim.vcomponents.all;
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entity sim_jtag is
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end sim_jtag;
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architecture behaviour of sim_jtag is
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begin
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jtag: process
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-- Global JTAG signals (used by BSCANE2 inside dmi_dtm
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alias j : glob_jtag_t is glob_jtag;
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-- Super fast JTAG clock for sim. For debugging the JTAG module,
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-- change this to something much larger, for example 60ns, to reflect
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-- more realistic conditions.
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constant jclk_period : time := 1 ns;
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-- Polling the socket... this could be made slower when nothing
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-- is connected once we have that indication from the C code.
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constant poll_period : time := 100 ns;
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-- Number of dummy JTAG clocks to inject after a command. (I haven't
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-- got that working with UrJtag but at least with sim, having the
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-- right number here allows the synchronizers time to complete a
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-- command on the first message exchange, thus avoiding the need
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-- for two full shifts for a response.
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constant dummy_clocks : integer := 80;
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procedure clock(count: in INTEGER) is
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begin
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for i in 1 to count loop
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j.tck <= '0';
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wait for jclk_period/2;
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j.tck <= '1';
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wait for jclk_period/2;
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end loop;
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end procedure clock;
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procedure clock_command(cmd: in std_ulogic_vector;
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rsp: out std_ulogic_vector) is
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begin
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j.capture <= '1';
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clock(1);
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j.capture <= '0';
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clock(1);
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j.shift <= '1';
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for i in 0 to cmd'length-1 loop
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j.tdi <= cmd(i);
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rsp := rsp(1 to rsp'length-1) & j.tdo;
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clock(1);
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end loop;
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j.shift <= '0';
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j.update <= '1';
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clock(1);
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j.update <= '0';
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clock(1);
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end procedure clock_command;
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variable cmd : std_ulogic_vector(0 to 247);
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variable rsp : std_ulogic_vector(0 to 247);
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variable msize : std_ulogic_vector(7 downto 0);
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variable size : integer;
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begin
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-- init & reset
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j.reset <= '1';
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j.sel <= "0000";
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j.capture <= '0';
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j.update <= '0';
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j.shift <= '0';
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j.tdi <= '0';
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j.tms <= '0';
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j.runtest <= '0';
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clock(5);
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j.reset <= '0';
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clock(5);
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-- select chain USER2
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-- XXX TODO: Send that via protocol instead
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-- XXX TODO: Also maybe have the C code tell us if connected or not
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-- and clock when connected.
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j.sel <= "0010";
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clock(1);
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rsp := (others => '0');
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while true loop
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wait for poll_period;
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sim_jtag_read_msg(cmd, msize);
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size := to_integer(unsigned(msize));
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if size /= 0 and size < 248 then
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clock_command(cmd(0 to size-1),
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rsp(0 to size-1));
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sim_jtag_write_msg(rsp, msize);
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clock(dummy_clocks);
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end if;
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end loop;
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end process;
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end;
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