Anton Blanchard 0a0ad9b384 Rebuild hello world assuming a 50MHz clock ...

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

2019-08-26 22:09:28 +10:00

..

clk_gen_bypass.vhd

Add dummy clock generator

2019-08-23 13:17:35 +02:00

clk_gen_plle2.vhd

Add and use plle2 primitive for nexys boards

2019-08-26 13:44:50 +02:00

firmware.hex

Add a few more FPGA related files

2019-08-23 16:23:53 +10:00

hello_world.hex

Rebuild hello world assuming a 50MHz clock

2019-08-26 22:09:28 +10:00

LICENSE

Initial import of microwatt

2019-08-22 16:46:13 +10:00

nexys_a7.xdc

Add constraint file for Nexys A7

2019-08-23 13:19:11 +02:00

nexys-video.xdc

Initial import of microwatt

2019-08-22 16:46:13 +10:00

nodivide.patch

Add a few more FPGA related files

2019-08-23 16:23:53 +10:00

pp_fifo.vhd

Initial import of microwatt

2019-08-22 16:46:13 +10:00

pp_soc_memory.vhd

Expose ram init file and memory size through toplevel

2019-08-23 13:18:39 +02:00

pp_soc_reset.vhd

Initial import of microwatt

2019-08-22 16:46:13 +10:00

pp_soc_uart.vhd

Initial import of microwatt

2019-08-22 16:46:13 +10:00

pp_utilities.vhd

Initial import of microwatt

2019-08-22 16:46:13 +10:00

toplevel.vhd

Expose ram init file and memory size through toplevel

2019-08-23 13:18:39 +02:00