mirror of
https://github.com/antonblanchard/microwatt.git
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d5bc6c8824
This adds a divider unit, connected to the core in much the same way that the multiplier unit is connected. The division algorithm is very simple-minded, taking 64 clock cycles for any division (even 32-bit division instructions). The decoding is simplified by making use of regularities in the instruction encoding for div* and mod* instructions. Instead of having PPC_* encodings from the first-stage decoder for each of the different div* and mod* instructions, we now just have PPC_DIV and PPC_MOD, and the inputs to the divider that indicate what sort of division operation to do are derived from instruction word bits. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
100 lines
3.3 KiB
VHDL
100 lines
3.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity writeback is
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port (
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clk : in std_ulogic;
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e_in : in Execute2ToWritebackType;
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l_in : in Loadstore2ToWritebackType;
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m_in : in MultiplyToWritebackType;
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d_in : in DividerToWritebackType;
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w_out : out WritebackToRegisterFileType;
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c_out : out WritebackToCrFileType;
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complete_out : out std_ulogic
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);
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end entity writeback;
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architecture behaviour of writeback is
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begin
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writeback_1: process(all)
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variable x : std_ulogic_vector(0 downto 0);
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variable y : std_ulogic_vector(0 downto 0);
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variable z : std_ulogic_vector(0 downto 0);
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variable w : std_ulogic_vector(0 downto 0);
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begin
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x := "" & e_in.valid;
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y := "" & l_in.valid;
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z := "" & m_in.valid;
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w := "" & d_in.valid;
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assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z)) + to_integer(unsigned(w))) <= 1 severity failure;
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x := "" & e_in.write_enable;
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y := "" & l_in.write_enable;
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z := "" & m_in.write_reg_enable;
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w := "" & d_in.write_reg_enable;
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assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z)) + to_integer(unsigned(w))) <= 1 severity failure;
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x := "" & e_in.write_cr_enable;
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y := "" & m_in.write_cr_enable;
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z := "" & d_in.write_cr_enable;
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assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1 severity failure;
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w_out <= WritebackToRegisterFileInit;
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c_out <= WritebackToCrFileInit;
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complete_out <= '0';
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if e_in.valid = '1' or l_in.valid = '1' or m_in.valid = '1' or d_in.valid = '1' then
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complete_out <= '1';
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end if;
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if e_in.write_enable = '1' then
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w_out.write_reg <= e_in.write_reg;
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w_out.write_data <= e_in.write_data;
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w_out.write_enable <= '1';
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end if;
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if e_in.write_cr_enable = '1' then
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c_out.write_cr_enable <= '1';
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c_out.write_cr_mask <= e_in.write_cr_mask;
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c_out.write_cr_data <= e_in.write_cr_data;
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end if;
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if l_in.write_enable = '1' then
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w_out.write_reg <= l_in.write_reg;
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w_out.write_data <= l_in.write_data;
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w_out.write_enable <= '1';
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end if;
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if m_in.write_reg_enable = '1' then
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w_out.write_enable <= '1';
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w_out.write_reg <= m_in.write_reg_nr;
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w_out.write_data <= m_in.write_reg_data;
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end if;
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if m_in.write_cr_enable = '1' then
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c_out.write_cr_enable <= '1';
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c_out.write_cr_mask <= m_in.write_cr_mask;
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c_out.write_cr_data <= m_in.write_cr_data;
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end if;
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if d_in.write_reg_enable = '1' then
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w_out.write_enable <= '1';
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w_out.write_reg <= d_in.write_reg_nr;
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w_out.write_data <= d_in.write_reg_data;
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end if;
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if d_in.write_cr_enable = '1' then
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c_out.write_cr_enable <= '1';
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c_out.write_cr_mask <= d_in.write_cr_mask;
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c_out.write_cr_data <= d_in.write_cr_data;
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end if;
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end process;
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end;
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