mirror of
https://github.com/antonblanchard/microwatt.git
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c9a2076dd3
For multiply and divide operations, execute1 now records the destination GPR number, RC and OE from the instruction, and the XER value. This means that the multiply and divide units don't need to record those values and then send them back to execute1. This makes the interface to those units a bit simpler. They simply report an overflow signal along with the result value, and execute1 takes care of updating XER if necessary. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
554 lines
22 KiB
VHDL
554 lines
22 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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use work.glibc_random.all;
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use work.ppc_fx_insns.all;
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entity divider_tb is
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end divider_tb;
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architecture behave of divider_tb is
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signal clk : std_ulogic;
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signal rst : std_ulogic;
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constant clk_period : time := 10 ns;
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signal d1 : Execute1ToDividerType;
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signal d2 : DividerToExecute1Type;
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begin
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divider_0: entity work.divider
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port map (clk => clk, rst => rst, d_in => d1, d_out => d2);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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stim_process: process
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variable ra, rb, rt, behave_rt: std_ulogic_vector(63 downto 0);
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variable si: std_ulogic_vector(15 downto 0);
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variable d128: std_ulogic_vector(127 downto 0);
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variable q128: std_ulogic_vector(127 downto 0);
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variable q64: std_ulogic_vector(63 downto 0);
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variable rem32: std_ulogic_vector(31 downto 0);
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begin
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rst <= '1';
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wait for clk_period;
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rst <= '0';
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d1.valid <= '1';
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d1.dividend <= x"0000000010001000";
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d1.divisor <= x"0000000000001111";
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d1.is_signed <= '0';
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d1.is_32bit <= '0';
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d1.is_extended <= '0';
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d1.is_modulus <= '0';
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d1.neg_result <= '0';
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wait for clk_period;
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assert d2.valid = '0';
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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assert d2.write_reg_data = x"000000000000f001" report "result " & to_hstring(d2.write_reg_data);
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wait for clk_period;
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assert d2.valid = '0' report "valid";
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d1.valid <= '1';
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wait for clk_period;
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assert d2.valid = '0' report "valid";
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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assert d2.write_reg_data = x"000000000000f001" report "result " & to_hstring(d2.write_reg_data);
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wait for clk_period;
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assert d2.valid = '0';
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-- test divd
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report "test divd";
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divd_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63) xor rb(63);
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" and (ra /= x"8000000000000000" or rb /= x"ffffffffffffffff") then
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behave_rt := ppc_divd(ra, rb);
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end if;
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assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data)
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report "bad divd expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
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end loop;
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end loop;
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end loop;
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-- test divdu
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report "test divdu";
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divdu_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '0';
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d1.neg_result <= '0';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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behave_rt := ppc_divdu(ra, rb);
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end if;
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assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data)
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report "bad divdu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
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end loop;
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end loop;
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end loop;
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-- test divde
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report "test divde";
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divde_loop : for vlength in 1 to 8 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63) xor rb(63);
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d1.is_extended <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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d128 := ra & x"0000000000000000";
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q128 := std_ulogic_vector(signed(d128) / signed(rb));
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if q128(127 downto 63) = x"0000000000000000" & '0' or
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q128(127 downto 63) = x"ffffffffffffffff" & '1' then
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behave_rt := q128(63 downto 0);
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end if;
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end if;
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assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data)
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report "bad divde expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
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end loop;
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end loop;
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end loop;
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-- test divdeu
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report "test divdeu";
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divdeu_loop : for vlength in 1 to 8 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '0';
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d1.neg_result <= '0';
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d1.is_extended <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if unsigned(rb) > unsigned(ra) then
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d128 := ra & x"0000000000000000";
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q128 := std_ulogic_vector(unsigned(d128) / unsigned(rb));
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behave_rt := q128(63 downto 0);
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end if;
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assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data)
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report "bad divdeu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
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end loop;
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end loop;
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end loop;
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-- test divw
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report "test divw";
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divw_loop : for dlength in 1 to 4 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63) xor rb(63);
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d1.is_extended <= '0';
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" and (ra /= x"ffffffff80000000" or rb /= x"ffffffffffffffff") then
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behave_rt := ppc_divw(ra, rb);
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end if;
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assert behave_rt = d2.write_reg_data
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report "bad divw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
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end loop;
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end loop;
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end loop;
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-- test divwu
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report "test divwu";
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divwu_loop : for dlength in 1 to 4 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '0';
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d1.neg_result <= '0';
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d1.is_extended <= '0';
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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behave_rt := ppc_divwu(ra, rb);
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end if;
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assert behave_rt = d2.write_reg_data
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report "bad divwu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
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end loop;
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end loop;
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end loop;
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-- test divwe
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report "test divwe";
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divwe_loop : for vlength in 1 to 4 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 32)) & x"00000000";
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63) xor rb(63);
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d1.is_extended <= '0';
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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q64 := std_ulogic_vector(signed(ra) / signed(rb));
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if q64(63 downto 31) = x"00000000" & '0' or
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q64(63 downto 31) = x"ffffffff" & '1' then
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behave_rt := x"00000000" & q64(31 downto 0);
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end if;
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assert behave_rt = d2.write_reg_data
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report "bad divwe expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
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end if;
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end loop;
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end loop;
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end loop;
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-- test divweu
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report "test divweu";
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divweu_loop : for vlength in 1 to 4 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 32)) & x"00000000";
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rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '0';
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d1.neg_result <= '0';
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d1.is_extended <= '0';
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if unsigned(rb(31 downto 0)) > unsigned(ra(63 downto 32)) then
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behave_rt := std_ulogic_vector(unsigned(ra) / unsigned(rb));
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end if;
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assert behave_rt = d2.write_reg_data
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report "bad divweu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
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end loop;
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end loop;
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end loop;
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-- test modsd
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report "test modsd";
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modsd_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63);
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d1.is_extended <= '0';
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d1.is_32bit <= '0';
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d1.is_modulus <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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behave_rt := std_ulogic_vector(signed(ra) rem signed(rb));
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end if;
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assert behave_rt = d2.write_reg_data
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report "bad modsd expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
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end loop;
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end loop;
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end loop;
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-- test modud
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report "test modud";
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modud_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '0';
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d1.neg_result <= '0';
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d1.is_extended <= '0';
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d1.is_32bit <= '0';
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d1.is_modulus <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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behave_rt := std_ulogic_vector(unsigned(ra) rem unsigned(rb));
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end if;
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assert behave_rt = d2.write_reg_data
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report "bad modud expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
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end loop;
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end loop;
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end loop;
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-- test modsw
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report "test modsw";
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modsw_loop : for dlength in 1 to 4 loop
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for vlength in 1 to dlength loop
|
|
for i in 0 to 100 loop
|
|
ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
|
|
rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
|
|
|
|
d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
|
|
d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
|
|
d1.is_signed <= '1';
|
|
d1.neg_result <= ra(63);
|
|
d1.is_extended <= '0';
|
|
d1.is_32bit <= '1';
|
|
d1.is_modulus <= '1';
|
|
d1.valid <= '1';
|
|
|
|
wait for clk_period;
|
|
|
|
d1.valid <= '0';
|
|
for j in 0 to 66 loop
|
|
wait for clk_period;
|
|
if d2.valid = '1' then
|
|
exit;
|
|
end if;
|
|
end loop;
|
|
assert d2.valid = '1';
|
|
|
|
behave_rt := (others => '0');
|
|
if rb /= x"0000000000000000" then
|
|
rem32 := std_ulogic_vector(signed(ra(31 downto 0)) rem signed(rb(31 downto 0)));
|
|
if rem32(31) = '0' then
|
|
behave_rt := x"00000000" & rem32;
|
|
else
|
|
behave_rt := x"ffffffff" & rem32;
|
|
end if;
|
|
end if;
|
|
assert behave_rt = d2.write_reg_data
|
|
report "bad modsw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
|
|
end loop;
|
|
end loop;
|
|
end loop;
|
|
|
|
-- test moduw
|
|
report "test moduw";
|
|
moduw_loop : for dlength in 1 to 4 loop
|
|
for vlength in 1 to dlength loop
|
|
for i in 0 to 100 loop
|
|
ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
|
|
rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
|
|
|
|
d1.dividend <= ra;
|
|
d1.divisor <= rb;
|
|
d1.is_signed <= '0';
|
|
d1.neg_result <= '0';
|
|
d1.is_extended <= '0';
|
|
d1.is_32bit <= '1';
|
|
d1.is_modulus <= '1';
|
|
d1.valid <= '1';
|
|
|
|
wait for clk_period;
|
|
|
|
d1.valid <= '0';
|
|
for j in 0 to 66 loop
|
|
wait for clk_period;
|
|
if d2.valid = '1' then
|
|
exit;
|
|
end if;
|
|
end loop;
|
|
assert d2.valid = '1';
|
|
|
|
behave_rt := (others => '0');
|
|
if rb /= x"0000000000000000" then
|
|
behave_rt := x"00000000" & std_ulogic_vector(unsigned(ra(31 downto 0)) rem unsigned(rb(31 downto 0)));
|
|
end if;
|
|
assert behave_rt(31 downto 0) = d2.write_reg_data(31 downto 0)
|
|
report "bad moduw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
|
|
end loop;
|
|
end loop;
|
|
end loop;
|
|
|
|
assert false report "end of test" severity failure;
|
|
wait;
|
|
end process;
|
|
end behave;
|