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174378b190
This makes the BRAMs use an output buffer, introducing an extra cycle latency. Without this, Vivado won't make timing at 100Mhz. We stash all the necessary response data in delayed latches, the extra cycle is NOT a state in the state machine, thus it's fully pipelined and doesn't involve stalling. This introduces an extra non-pipelined cycle for loads with update to avoid collision on the writeback output between the now delayed load data and the register update. We could avoid it by moving the register update in the pipeline bubble created by the extra update state, but it's a bit trickier, so I leave that for a latter optimization. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
87 lines
2.1 KiB
VHDL
87 lines
2.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity cache_ram is
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generic(
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ROW_BITS : integer := 16;
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WIDTH : integer := 64;
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TRACE : boolean := false;
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ADD_BUF : boolean := false
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);
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port(
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clk : in std_logic;
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rd_en : in std_logic;
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rd_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
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rd_data : out std_logic_vector(WIDTH - 1 downto 0);
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wr_en : in std_logic;
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wr_sel : in std_logic_vector(WIDTH/8 - 1 downto 0);
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wr_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
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wr_data : in std_logic_vector(WIDTH - 1 downto 0)
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);
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end cache_ram;
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architecture rtl of cache_ram is
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constant SIZE : integer := 2**ROW_BITS;
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type ram_type is array (0 to SIZE - 1) of std_logic_vector(WIDTH - 1 downto 0);
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signal ram : ram_type;
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attribute ram_style : string;
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attribute ram_style of ram : signal is "block";
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attribute ram_decomp : string;
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attribute ram_decomp of ram : signal is "power";
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signal rd_data0 : std_logic_vector(WIDTH - 1 downto 0);
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begin
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process(clk)
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variable lbit : integer range 0 to WIDTH - 1;
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variable mbit : integer range 0 to WIDTH - 1;
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variable widx : integer range 0 to SIZE - 1;
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begin
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if rising_edge(clk) then
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if wr_en = '1' then
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if TRACE then
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report "write a:" & to_hstring(wr_addr) &
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" sel:" & to_hstring(wr_sel) &
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" dat:" & to_hstring(wr_data);
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end if;
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for i in 0 to WIDTH/8-1 loop
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lbit := i * 8;
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mbit := lbit + 7;
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widx := to_integer(unsigned(wr_addr));
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if wr_sel(i) = '1' then
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ram(widx)(mbit downto lbit) <= wr_data(mbit downto lbit);
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end if;
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end loop;
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end if;
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if rd_en = '1' then
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rd_data0 <= ram(to_integer(unsigned(rd_addr)));
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if TRACE then
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report "read a:" & to_hstring(rd_addr) &
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" dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
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end if;
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end if;
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end if;
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end process;
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buf: if ADD_BUF generate
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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rd_data <= rd_data0;
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end if;
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end process;
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end generate;
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nobuf: if not ADD_BUF generate
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begin
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rd_data <= rd_data0;
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end generate;
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end;
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