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f5424f8e71
Micropython has been able to fit into 384kB for ages, so lets reduce our simulated RAM. This is useful for testing if micropython will run on an ECP5 85k, which has enough BRAM for 384kB but not enough for 512kB. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
51 lines
839 B
VHDL
51 lines
839 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity core_tb is
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end core_tb;
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architecture behave of core_tb is
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signal clk, rst: std_logic;
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-- testbench signals
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constant clk_period : time := 10 ns;
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begin
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soc0: entity work.soc
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generic map(
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SIM => true,
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MEMORY_SIZE => (384*1024),
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RAM_INIT_FILE => "main_ram.bin",
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RESET_LOW => false
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)
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port map(
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rst => rst,
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system_clk => clk,
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uart0_rxd => '0',
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uart0_txd => open
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);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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rst_process: process
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begin
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rst <= '1';
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wait for 10*clk_period;
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rst <= '0';
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wait;
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end process;
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jtag: entity work.sim_jtag;
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end;
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