github.com/antonblanchard.microwatt
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8bb3c8f8b6e71935cf9acceaa2139f6d68024975
antonblanchard.microwatt/fpga
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Benjamin Herrenschmidt 8bb3c8f8b6 soc: Add DRAM address decoding 
Still not attached to any board

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-08 11:41:06 +10:00
..
arty_a7.xdc
Add SPI configuration to Xilinx constraint files
2019-12-09 16:12:37 +11:00
clk_gen_bypass.vhd
Fix clk_gen_bypass
2019-10-13 14:41:53 +11:00
clk_gen_mcmm.vhd
Improve PLL/MMCM clocks configuration
2019-09-30 13:57:36 +10:00
clk_gen_plle2.vhd
Improve PLL/MMCM clocks configuration
2019-09-30 13:57:36 +10:00
cmod_a7-35.xdc
Add SPI configuration to Xilinx constraint files
2019-12-09 16:12:37 +11:00
firmware.hex
Add a few more FPGA related files
2019-08-23 16:23:53 +10:00
hello_world.hex
Update hello_world for 100Mhz clock
2020-05-08 11:41:06 +10:00
LICENSE
Initial import of microwatt
2019-08-22 16:46:13 +10:00
main_bram.vhdl
Fix some ghdlsynth issues with fpga_bram
2020-01-11 14:34:25 +11:00
nexys_a7.xdc
Add SPI configuration to Xilinx constraint files
2019-12-09 16:12:37 +11:00
nexys-video.xdc
Add SPI configuration to Xilinx constraint files
2019-12-09 16:12:37 +11:00
pp_fifo.vhd
fifo: Reformat
2019-10-13 12:57:23 +11:00
pp_soc_uart.vhd
Add a few FFs on the RX input to avoid metastability issues
2020-01-19 22:34:24 +11:00
pp_utilities.vhd
Initial import of microwatt
2019-08-22 16:46:13 +10:00
soc_reset_tb.vhdl
Rework SOC reset
2019-09-08 07:40:19 +10:00
soc_reset.vhdl
Rework SOC reset
2019-09-08 07:40:19 +10:00
toplevel.vhdl
soc: Add DRAM address decoding
2020-05-08 11:41:06 +10:00