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9646fe28b0
This makes the exts[bhw] instructions do the sign extension in the writeback stage using the sign-extension logic there instead of having unique sign extension logic in execute1. This requires passing the data length and sign extend flag from decode2 down through execute1 and execute2 and into writeback. As a side bonus we reduce the number of values in insn_type_t by two. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
53 lines
1.2 KiB
VHDL
53 lines
1.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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-- 2 cycle ALU
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-- We handle rc form instructions here
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entity execute2 is
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port (
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clk : in std_ulogic;
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e_in : in Execute1ToExecute2Type;
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e_out : out Execute2ToWritebackType
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);
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end execute2;
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architecture behave of execute2 is
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signal r, rin : Execute2ToWritebackType;
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begin
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execute2_0: process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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end if;
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end process;
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execute2_1: process(all)
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variable v : Execute2ToWritebackType;
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begin
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v := rin;
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v.valid := e_in.valid;
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v.write_enable := e_in.write_enable;
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v.write_reg := e_in.write_reg;
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v.write_data := e_in.write_data;
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v.write_cr_enable := e_in.write_cr_enable;
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v.write_cr_mask := e_in.write_cr_mask;
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v.write_cr_data := e_in.write_cr_data;
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v.rc := e_in.rc;
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v.write_len := e_in.write_len;
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v.sign_extend := e_in.sign_extend;
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-- Update registers
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rin <= v;
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-- Update outputs
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e_out <= r;
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end process;
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end;
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