Matt Johnston 9c64f8a98b mw_debug: Add Lattice ECP5 support ...

"-b ecp5" will select ECP5 interface that talks to a JTAGG
primitive.

For example with a FT232H JTAG board:

./mw_debug  -t 'ft2232 vid=0x0403 pid=0x6014'  -s 30000000 -b ecp5 mr ff003888 6
Connected to libftdi driver.
Found device ID: 0x41113043
00000000ff003888: 6d6f636c65570a0a  ..Welcom
00000000ff003890: 63694d206f742065  e to Mic
00000000ff003898: 2120747461776f72  rowatt !
00000000ff0038a0: 0000000000000a0a  ........
00000000ff0038a8: 67697320636f5320   Soc sig
00000000ff0038b0: 203a65727574616e  nature:
Core: running
 NIA: c0000000000187f8
 MSR: 9000000000001033

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>

2022-02-07 13:37:51 +08:00

..

fmt_log

decode: Add a facility field to the instruction decode tables

2021-01-15 12:40:09 +11:00

mw_debug

mw_debug: Add Lattice ECP5 support

2022-02-07 13:37:51 +08:00

bin2hex.py

bin2hex: Make sure to generate little endian files

2020-06-02 19:56:08 +10:00

dependencies.py

uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl

2020-06-24 09:53:46 +10:00

gen_icache_tb.py

icache_tb: Improve test and include test file

2019-10-18 16:41:05 +11:00

run_test_console.sh

Add test cases for new exceptions and supervisor state

2020-04-01 12:02:33 +11:00

run_test.sh

Dump CTR, LR and CR on sim termination, and update our tests

2020-01-11 11:09:38 +11:00

test_micropython_long.py

Update micropython

2020-01-19 21:36:38 +11:00

test_micropython_verilator_long.py

makefile: Add some verilator micropython tests

2021-08-14 19:36:29 +10:00

test_micropython_verilator.py

makefile: Add some verilator micropython tests

2021-08-14 19:36:29 +10:00

test_micropython.py

Update micropython

2020-01-19 21:36:38 +11:00

vhdltags

Add VHDL TAGS

2020-04-23 15:00:37 +10:00