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270d7b1b9a
This adds support for the Digilane Cmod A7-35. I had to use the MMCM because the clock (12 MHz) is below the PLL minimum of 19 MHz. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
9 lines
467 B
Tcl
9 lines
467 B
Tcl
## Clock signal 12 MHz
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set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
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create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {ext_clk}];
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set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }];
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set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }];
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set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ext_rst }];
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