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a6858f716a
In the fall of 2020, cmd/clk scan in liblitedram was changed in a way that required reverting cmd_latency being set to 1 in LiteDRAM commit 4e62d28 back to 0. For the default in s7ddrphy.py this revert happened in 496cd27, but for standalone gen the .yml was never updated in neither LiteDRAM nor Microwatt, leading to regression: https://github.com/antonblanchard/microwatt/issues/363 The present commit updates the .yml so DRAM works on Genesys2 again. See also https://github.com/enjoy-digital/litedram/pull/368 for a corresponding update to the .yml in LiteDRAM. Signed-off-by: Boris Shingarov <shingarov@labware.com>
38 lines
1.6 KiB
YAML
38 lines
1.6 KiB
YAML
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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{
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# General ------------------------------------------------------------------
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"cpu": "None", # CPU type (ex vexriscv, serv, None)
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"speedgrade": -2, # FPGA speedgrade
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"memtype": "DDR3", # DRAM type
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# PHY ----------------------------------------------------------------------
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"cmd_latency": 0, # Command additional latency
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"sdram_module": "MT41J256M16", # SDRAM modules of the board or SO-DIMM
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"sdram_module_nb": 4, # Number of byte groups
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"sdram_rank_nb": 1, # Number of ranks
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"sdram_phy": "K7DDRPHY", # Type of FPGA PHY
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# Electrical ---------------------------------------------------------------
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"rtt_nom": "60ohm", # Nominal termination
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"rtt_wr": "60ohm", # Write termination
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"ron": "34ohm", # Output driver impedance
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# Frequency ----------------------------------------------------------------
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"input_clk_freq": 200e6, # Input clock frequency
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"sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
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"iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
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# Core ---------------------------------------------------------------------
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"cmd_buffer_depth": 16, # Depth of the command buffer
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# User Ports ---------------------------------------------------------------
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"user_ports": {
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"native_0": {
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"type": "native",
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"block_until_ready": False,
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},
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},
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}
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