Benjamin Herrenschmidt a93d9e77c9 litedram: Remove remnants of riscv-inits ...

We still had some wires bringing an extra serial port out of
litedram for the built-in riscv processor. This is all gone now
so take them out.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

2020-06-10 13:10:57 +10:00

..

fusesoc-add-files.py

litedram: Remove old "VexRiscV" based initializations

2020-06-05 11:23:04 +10:00

litedram-wrapper-l2.vhdl

litedram: Remove remnants of riscv-inits

2020-06-10 13:10:57 +10:00

sim_dram_verilate.mk

litedram: Add simulation support

2020-06-05 10:24:47 +10:00

sim_litedram_c.cpp

litedram: Add simulation support

2020-06-05 10:24:47 +10:00

sim_litedram.vhdl

litedram: Add simulation support

2020-06-05 10:24:47 +10:00

wave_tb.gtkw

litedram: Test bench

2020-06-05 10:33:27 +10:00

wave.gtkw

litedram: Add an L2 cache with store queue

2020-06-05 10:33:27 +10:00

wave.opt

litedram: Add an L2 cache with store queue

2020-06-05 10:33:27 +10:00