Benjamin Herrenschmidt b23fd6c5f1 litedram: Defer clearing of tags & valids to improve timing ...

Currently, there's a huge mux gathering the output of all the PLRUs
to select the victim way on cache miss. This is fed combinationally
into the clearing of the valid and tags.

In order to help timing, let's store it instead and perform the
clearing on the next cycle. The L2 doesn't respond to requests
when not in IDLE state so this should have no negative effects.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

2020-06-12 21:01:34 +10:00

..

fusesoc-add-files.py

litedram: Remove old "VexRiscV" based initializations

2020-06-05 11:23:04 +10:00

litedram-wrapper-l2.vhdl

litedram: Defer clearing of tags & valids to improve timing

2020-06-12 21:01:34 +10:00

sim_dram_verilate.mk

litedram: Add simulation support

2020-06-05 10:24:47 +10:00

sim_litedram_c.cpp

litedram: Add simulation support

2020-06-05 10:24:47 +10:00

sim_litedram.vhdl

litedram: Add simulation support

2020-06-05 10:24:47 +10:00

wave_tb.gtkw

litedram: Test bench

2020-06-05 10:33:27 +10:00

wave.gtkw

litedram: Add an L2 cache with store queue

2020-06-05 10:33:27 +10:00

wave.opt

litedram: Add an L2 cache with store queue

2020-06-05 10:33:27 +10:00