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antonblanchard.microwatt/litedram/extras
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Benjamin Herrenschmidt b58ff724f6 litedram: Add stash buffer to the L2 cache wishbone interface 
This breaks the long stall signal coming back to the processor
and helps improve overall timing.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-06-12 21:01:34 +10:00
..
fusesoc-add-files.py
litedram: Remove old "VexRiscV" based initializations
2020-06-05 11:23:04 +10:00
litedram-wrapper-l2.vhdl
litedram: Add stash buffer to the L2 cache wishbone interface
2020-06-12 21:01:34 +10:00
sim_dram_verilate.mk
litedram: Add simulation support
2020-06-05 10:24:47 +10:00
sim_litedram_c.cpp
litedram: Add simulation support
2020-06-05 10:24:47 +10:00
sim_litedram.vhdl
litedram: Add simulation support
2020-06-05 10:24:47 +10:00
wave_tb.gtkw
litedram: Test bench
2020-06-05 10:33:27 +10:00
wave.gtkw
litedram: Add an L2 cache with store queue
2020-06-05 10:33:27 +10:00
wave.opt
litedram: Add an L2 cache with store queue
2020-06-05 10:33:27 +10:00