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https://github.com/antonblanchard/microwatt.git
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cc4dcb3597
This adds an SPI flash controller which supports direct memory-mapped access to the flash along with a manual mode to send commands. The direct mode can be set via generic to default to single wire or quad mode. The controller supports normal, dual and quad accesses with configurable commands, clock divider, dummy clocks etc... The SPI clock can be an even divider of sys_clk starting at 2 (so max 50Mhz with our typical Arty designs). A flash offset is carried via generics to syscon to tell SW about which portion of the flash is reserved for the FPGA bitfile. There is currently no plumbing to make the CPU reset past that address (TBD). Note: Operating at 50Mhz has proven unreliable without adding some delay to the sampling of the input data. I'm working in improving this, in the meantime, I'm leaving the default set at 25 Mhz. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
82 lines
1.8 KiB
VHDL
82 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity core_tb is
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end core_tb;
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architecture behave of core_tb is
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signal clk, rst: std_logic;
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-- testbench signals
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constant clk_period : time := 10 ns;
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-- Dummy DRAM
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signal wb_dram_in : wishbone_master_out;
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signal wb_dram_out : wishbone_slave_out;
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signal wb_dram_ctrl_in : wb_io_master_out;
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signal wb_dram_ctrl_out : wb_io_slave_out;
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-- Dummy SPI
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signal spi_sdat_i : std_ulogic_vector(0 downto 0);
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begin
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soc0: entity work.soc
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generic map(
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SIM => true,
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MEMORY_SIZE => (384*1024),
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RAM_INIT_FILE => "main_ram.bin",
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RESET_LOW => false,
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CLK_FREQ => 100000000,
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HAS_SPI_FLASH => false
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)
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port map(
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rst => rst,
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system_clk => clk,
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uart0_rxd => '0',
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uart0_txd => open,
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spi_flash_sck => open,
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spi_flash_cs_n => open,
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spi_flash_sdat_o => open,
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spi_flash_sdat_oe => open,
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spi_flash_sdat_i => spi_sdat_i,
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wb_dram_in => wb_dram_in,
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wb_dram_out => wb_dram_out,
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wb_dram_ctrl_in => wb_dram_ctrl_in,
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wb_dram_ctrl_out => wb_dram_ctrl_out,
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alt_reset => '0'
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);
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spi_sdat_i(0) <= '1';
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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rst_process: process
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begin
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rst <= '1';
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wait for 10*clk_period;
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rst <= '0';
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wait;
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end process;
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jtag: entity work.sim_jtag;
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-- Dummy DRAM
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wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
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wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
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wb_dram_out.stall <= '0';
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wb_dram_ctrl_out.ack <= wb_dram_ctrl_in.cyc and wb_dram_ctrl_in.stb;
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wb_dram_ctrl_out.dat <= x"FFFFFFFF";
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wb_dram_ctrl_out.stall <= '0';
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end;
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