Paul Mackerras b8f9c833f8 litedram: Split L2 PLRU into storage and logic ...

As has been done for the L1 dcache and icache, this puts the L2 cache
PLRU state into a little RAM and has a single copy of the logic to
calculate the pseudo-LRU way and update the PLRU state.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

2022-09-19 18:05:30 +10:00

..

fusesoc-add-files.py

litedram: Remove old "VexRiscV" based initializations

2020-06-05 11:23:04 +10:00

litedram-wrapper-l2.vhdl

litedram: Split L2 PLRU into storage and logic

2022-09-19 18:05:30 +10:00

sim_dram_verilate.mk

litedram: Add simulation support

2020-06-05 10:24:47 +10:00

sim_litedram_c.cpp

Fix build of core_dram_tb and dram_tb and fix tracing

2022-09-05 00:24:51 +10:00

sim_litedram.vhdl

Extend LiteDRAM VHDL wrapper to allow more than one clock line

2022-02-23 16:33:08 -06:00

wave_tb.gtkw

litedram: l2: Latency improvements

2020-07-08 16:47:30 +10:00

wave.gtkw

litedram: Add an L2 cache with store queue

2020-06-05 10:33:27 +10:00

wave.opt

litedram: Add an L2 cache with store queue

2020-06-05 10:33:27 +10:00