mirror of
https://github.com/antonblanchard/microwatt.git
synced 2026-02-18 13:27:06 +00:00
45cd8f4fc3
This extends the register file so it can hold FPR values, and implements the FP loads and stores that do not require conversion between single and double precision. We now have the FP, FE0 and FE1 bits in MSR. FP loads and stores cause a FP unavailable interrupt if MSR[FP] = 0. The FPU facilities are optional and their presence is controlled by the HAS_FPU generic passed down from the top-level board file. It defaults to true for all except the A7-35 boards. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
522 lines
19 KiB
VHDL
522 lines
19 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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package common is
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-- Processor Version Number
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constant PVR_MICROWATT : std_ulogic_vector(31 downto 0) := x"00630000";
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-- MSR bit numbers
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constant MSR_SF : integer := (63 - 0); -- Sixty-Four bit mode
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constant MSR_EE : integer := (63 - 48); -- External interrupt Enable
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constant MSR_PR : integer := (63 - 49); -- PRoblem state
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constant MSR_FP : integer := (63 - 50); -- Floating Point available
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constant MSR_FE0 : integer := (63 - 52); -- Floating Exception mode
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constant MSR_SE : integer := (63 - 53); -- Single-step bit of TE field
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constant MSR_BE : integer := (63 - 54); -- Branch trace bit of TE field
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constant MSR_FE1 : integer := (63 - 55); -- Floating Exception mode
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constant MSR_IR : integer := (63 - 58); -- Instruction Relocation
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constant MSR_DR : integer := (63 - 59); -- Data Relocation
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constant MSR_RI : integer := (63 - 62); -- Recoverable Interrupt
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constant MSR_LE : integer := (63 - 63); -- Little Endian
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-- SPR numbers
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subtype spr_num_t is integer range 0 to 1023;
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function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
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constant SPR_XER : spr_num_t := 1;
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constant SPR_LR : spr_num_t := 8;
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constant SPR_CTR : spr_num_t := 9;
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constant SPR_TAR : spr_num_t := 815;
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constant SPR_DSISR : spr_num_t := 18;
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constant SPR_DAR : spr_num_t := 19;
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constant SPR_TB : spr_num_t := 268;
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constant SPR_TBU : spr_num_t := 269;
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constant SPR_DEC : spr_num_t := 22;
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constant SPR_SRR0 : spr_num_t := 26;
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constant SPR_SRR1 : spr_num_t := 27;
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constant SPR_CFAR : spr_num_t := 28;
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constant SPR_HSRR0 : spr_num_t := 314;
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constant SPR_HSRR1 : spr_num_t := 315;
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constant SPR_SPRG0 : spr_num_t := 272;
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constant SPR_SPRG1 : spr_num_t := 273;
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constant SPR_SPRG2 : spr_num_t := 274;
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constant SPR_SPRG3 : spr_num_t := 275;
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constant SPR_SPRG3U : spr_num_t := 259;
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constant SPR_HSPRG0 : spr_num_t := 304;
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constant SPR_HSPRG1 : spr_num_t := 305;
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constant SPR_PID : spr_num_t := 48;
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constant SPR_PRTBL : spr_num_t := 720;
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constant SPR_PVR : spr_num_t := 287;
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-- GPR indices in the register file (GPR only)
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subtype gpr_index_t is std_ulogic_vector(4 downto 0);
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-- Extended GPR index (can hold an SPR or a FPR)
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subtype gspr_index_t is std_ulogic_vector(6 downto 0);
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-- FPR indices
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subtype fpr_index_t is std_ulogic_vector(4 downto 0);
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-- Some SPRs are stored in the register file, they use the magic
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-- GPR numbers above 31.
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--
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-- The function fast_spr_num() returns the corresponding fast
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-- pseudo-GPR number for a given SPR number. The result MSB
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-- indicates if this is indeed a fast SPR. If clear, then
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-- the SPR is not stored in the GPR file.
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--
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-- FPRs are also stored in the register file, using GSPR
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-- numbers from 64 to 95.
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--
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function fast_spr_num(spr: spr_num_t) return gspr_index_t;
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-- Indices conversion functions
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function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
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function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
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function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
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function is_fast_spr(s: gspr_index_t) return std_ulogic;
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function fpr_to_gspr(f: fpr_index_t) return gspr_index_t;
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-- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
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-- in the CR file as a kind of CR extension (with a separate write
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-- control). The rest is stored as a fast SPR.
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type xer_common_t is record
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ca : std_ulogic;
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ca32 : std_ulogic;
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ov : std_ulogic;
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ov32 : std_ulogic;
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so : std_ulogic;
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end record;
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constant xerc_init : xer_common_t := (others => '0');
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type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
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-- For now, fixed 16 sources, make this either a parametric
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-- package of some sort or an unconstrainted array.
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type ics_to_icp_t is record
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-- Level interrupts only, ICS just keeps prsenting the
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-- highest priority interrupt. Once handling edge, something
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-- smarter involving handshake & reject support will be needed
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src : std_ulogic_vector(3 downto 0);
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pri : std_ulogic_vector(7 downto 0);
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end record;
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-- This needs to die...
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type ctrl_t is record
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tb: std_ulogic_vector(63 downto 0);
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dec: std_ulogic_vector(63 downto 0);
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msr: std_ulogic_vector(63 downto 0);
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cfar: std_ulogic_vector(63 downto 0);
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irq_state : irq_state_t;
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srr1: std_ulogic_vector(63 downto 0);
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end record;
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type Fetch1ToIcacheType is record
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req: std_ulogic;
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virt_mode : std_ulogic;
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priv_mode : std_ulogic;
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big_endian : std_ulogic;
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stop_mark: std_ulogic;
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sequential: std_ulogic;
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nia: std_ulogic_vector(63 downto 0);
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end record;
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type IcacheToDecode1Type is record
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valid: std_ulogic;
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stop_mark: std_ulogic;
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fetch_failed: std_ulogic;
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nia: std_ulogic_vector(63 downto 0);
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insn: std_ulogic_vector(31 downto 0);
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end record;
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type Decode1ToDecode2Type is record
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valid: std_ulogic;
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stop_mark : std_ulogic;
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nia: std_ulogic_vector(63 downto 0);
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insn: std_ulogic_vector(31 downto 0);
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ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
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ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
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decode: decode_rom_t;
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br_pred: std_ulogic; -- Branch was predicted to be taken
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end record;
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constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
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(valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
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ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init, br_pred => '0');
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type Decode1ToFetch1Type is record
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redirect : std_ulogic;
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redirect_nia : std_ulogic_vector(63 downto 0);
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end record;
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type Decode2ToExecute1Type is record
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valid: std_ulogic;
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unit : unit_t;
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insn_type: insn_type_t;
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nia: std_ulogic_vector(63 downto 0);
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write_reg: gspr_index_t;
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read_reg1: gspr_index_t;
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read_reg2: gspr_index_t;
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read_data1: std_ulogic_vector(63 downto 0);
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read_data2: std_ulogic_vector(63 downto 0);
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read_data3: std_ulogic_vector(63 downto 0);
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bypass_data1: std_ulogic;
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bypass_data2: std_ulogic;
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bypass_data3: std_ulogic;
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cr: std_ulogic_vector(31 downto 0);
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bypass_cr : std_ulogic;
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xerc: xer_common_t;
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lr: std_ulogic;
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rc: std_ulogic;
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oe: std_ulogic;
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invert_a: std_ulogic;
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invert_out: std_ulogic;
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input_carry: carry_in_t;
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output_carry: std_ulogic;
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input_cr: std_ulogic;
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output_cr: std_ulogic;
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is_32bit: std_ulogic;
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is_signed: std_ulogic;
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insn: std_ulogic_vector(31 downto 0);
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data_len: std_ulogic_vector(3 downto 0);
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byte_reverse : std_ulogic;
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sign_extend : std_ulogic; -- do we need to sign extend?
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update : std_ulogic; -- is this an update instruction?
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reserve : std_ulogic; -- set for larx/stcx
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br_pred : std_ulogic;
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end record;
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constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
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(valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
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bypass_cr => '0', lr => '0', rc => '0', oe => '0', invert_a => '0',
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invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
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is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
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byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'), read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'), cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'), others => (others => '0'));
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type MultiplyInputType is record
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valid: std_ulogic;
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data1: std_ulogic_vector(63 downto 0);
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data2: std_ulogic_vector(63 downto 0);
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addend: std_ulogic_vector(127 downto 0);
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is_32bit: std_ulogic;
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not_result: std_ulogic;
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end record;
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constant MultiplyInputInit : MultiplyInputType := (valid => '0',
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is_32bit => '0', not_result => '0',
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others => (others => '0'));
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type MultiplyOutputType is record
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valid: std_ulogic;
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result: std_ulogic_vector(127 downto 0);
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overflow : std_ulogic;
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end record;
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constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
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others => (others => '0'));
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type Execute1ToDividerType is record
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valid: std_ulogic;
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dividend: std_ulogic_vector(63 downto 0);
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divisor: std_ulogic_vector(63 downto 0);
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is_signed: std_ulogic;
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is_32bit: std_ulogic;
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is_extended: std_ulogic;
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is_modulus: std_ulogic;
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neg_result: std_ulogic;
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end record;
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constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
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is_extended => '0', is_modulus => '0',
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neg_result => '0', others => (others => '0'));
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type Decode2ToRegisterFileType is record
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read1_enable : std_ulogic;
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read1_reg : gspr_index_t;
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read2_enable : std_ulogic;
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read2_reg : gspr_index_t;
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read3_enable : std_ulogic;
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read3_reg : gspr_index_t;
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end record;
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type RegisterFileToDecode2Type is record
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read1_data : std_ulogic_vector(63 downto 0);
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read2_data : std_ulogic_vector(63 downto 0);
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read3_data : std_ulogic_vector(63 downto 0);
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end record;
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type Decode2ToCrFileType is record
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read : std_ulogic;
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end record;
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type CrFileToDecode2Type is record
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read_cr_data : std_ulogic_vector(31 downto 0);
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read_xerc_data : xer_common_t;
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end record;
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type Execute1ToFetch1Type is record
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redirect: std_ulogic;
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virt_mode: std_ulogic;
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priv_mode: std_ulogic;
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big_endian: std_ulogic;
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mode_32bit: std_ulogic;
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redirect_nia: std_ulogic_vector(63 downto 0);
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end record;
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constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
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priv_mode => '0', big_endian => '0',
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mode_32bit => '0', others => (others => '0'));
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type Execute1ToLoadstore1Type is record
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valid : std_ulogic;
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op : insn_type_t; -- what ld/st or m[tf]spr or TLB op to do
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nia : std_ulogic_vector(63 downto 0);
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insn : std_ulogic_vector(31 downto 0);
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addr1 : std_ulogic_vector(63 downto 0);
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addr2 : std_ulogic_vector(63 downto 0);
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data : std_ulogic_vector(63 downto 0); -- data to write, unused for read
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write_reg : gspr_index_t;
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length : std_ulogic_vector(3 downto 0);
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ci : std_ulogic; -- cache-inhibited load/store
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byte_reverse : std_ulogic;
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sign_extend : std_ulogic; -- do we need to sign extend?
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update : std_ulogic; -- is this an update instruction?
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update_reg : gpr_index_t; -- if so, the register to update
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xerc : xer_common_t;
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reserve : std_ulogic; -- set for larx/stcx.
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rc : std_ulogic; -- set for stcx.
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virt_mode : std_ulogic; -- do translation through TLB
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priv_mode : std_ulogic; -- privileged mode (MSR[PR] = 0)
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mode_32bit : std_ulogic; -- trim addresses to 32 bits
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end record;
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constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
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sign_extend => '0', update => '0', xerc => xerc_init,
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reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
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nia => (others => '0'), insn => (others => '0'),
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addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
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write_reg => (others => '0'), length => (others => '0'),
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mode_32bit => '0', others => (others => '0'));
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type Loadstore1ToExecute1Type is record
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busy : std_ulogic;
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exception : std_ulogic;
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alignment : std_ulogic;
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invalid : std_ulogic;
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perm_error : std_ulogic;
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rc_error : std_ulogic;
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badtree : std_ulogic;
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segment_fault : std_ulogic;
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instr_fault : std_ulogic;
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end record;
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type Loadstore1ToDcacheType is record
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valid : std_ulogic;
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load : std_ulogic; -- is this a load
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dcbz : std_ulogic;
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nc : std_ulogic;
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reserve : std_ulogic;
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virt_mode : std_ulogic;
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priv_mode : std_ulogic;
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addr : std_ulogic_vector(63 downto 0);
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data : std_ulogic_vector(63 downto 0);
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byte_sel : std_ulogic_vector(7 downto 0);
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end record;
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type DcacheToLoadstore1Type is record
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valid : std_ulogic;
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data : std_ulogic_vector(63 downto 0);
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store_done : std_ulogic;
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error : std_ulogic;
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cache_paradox : std_ulogic;
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end record;
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type Loadstore1ToMmuType is record
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valid : std_ulogic;
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tlbie : std_ulogic;
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slbia : std_ulogic;
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mtspr : std_ulogic;
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iside : std_ulogic;
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load : std_ulogic;
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priv : std_ulogic;
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sprn : std_ulogic_vector(9 downto 0);
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addr : std_ulogic_vector(63 downto 0);
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rs : std_ulogic_vector(63 downto 0);
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end record;
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type MmuToLoadstore1Type is record
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done : std_ulogic;
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err : std_ulogic;
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invalid : std_ulogic;
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badtree : std_ulogic;
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segerr : std_ulogic;
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perm_error : std_ulogic;
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rc_error : std_ulogic;
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sprval : std_ulogic_vector(63 downto 0);
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end record;
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type MmuToDcacheType is record
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valid : std_ulogic;
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tlbie : std_ulogic;
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doall : std_ulogic;
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tlbld : std_ulogic;
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addr : std_ulogic_vector(63 downto 0);
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pte : std_ulogic_vector(63 downto 0);
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end record;
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type DcacheToMmuType is record
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stall : std_ulogic;
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done : std_ulogic;
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err : std_ulogic;
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data : std_ulogic_vector(63 downto 0);
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end record;
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type MmuToIcacheType is record
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tlbld : std_ulogic;
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tlbie : std_ulogic;
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doall : std_ulogic;
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addr : std_ulogic_vector(63 downto 0);
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pte : std_ulogic_vector(63 downto 0);
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end record;
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type Loadstore1ToWritebackType is record
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valid : std_ulogic;
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write_enable: std_ulogic;
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write_reg : gspr_index_t;
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write_data : std_ulogic_vector(63 downto 0);
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xerc : xer_common_t;
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rc : std_ulogic;
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store_done : std_ulogic;
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end record;
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constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
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rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
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type Execute1ToWritebackType is record
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valid: std_ulogic;
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rc : std_ulogic;
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mode_32bit : std_ulogic;
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write_enable : std_ulogic;
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write_reg: gspr_index_t;
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write_data: std_ulogic_vector(63 downto 0);
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write_cr_enable : std_ulogic;
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write_cr_mask : std_ulogic_vector(7 downto 0);
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write_cr_data : std_ulogic_vector(31 downto 0);
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write_xerc_enable : std_ulogic;
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xerc : xer_common_t;
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exc_write_enable : std_ulogic;
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exc_write_reg : gspr_index_t;
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exc_write_data : std_ulogic_vector(63 downto 0);
|
|
end record;
|
|
constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', mode_32bit => '0', write_enable => '0',
|
|
write_cr_enable => '0', exc_write_enable => '0',
|
|
write_xerc_enable => '0', xerc => xerc_init,
|
|
write_data => (others => '0'), write_cr_mask => (others => '0'),
|
|
write_cr_data => (others => '0'), write_reg => (others => '0'),
|
|
exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
|
|
|
|
type DividerToExecute1Type is record
|
|
valid: std_ulogic;
|
|
write_reg_data: std_ulogic_vector(63 downto 0);
|
|
overflow : std_ulogic;
|
|
end record;
|
|
constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
|
|
others => (others => '0'));
|
|
|
|
type WritebackToRegisterFileType is record
|
|
write_reg : gspr_index_t;
|
|
write_data : std_ulogic_vector(63 downto 0);
|
|
write_enable : std_ulogic;
|
|
end record;
|
|
constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
|
|
|
|
type WritebackToCrFileType is record
|
|
write_cr_enable : std_ulogic;
|
|
write_cr_mask : std_ulogic_vector(7 downto 0);
|
|
write_cr_data : std_ulogic_vector(31 downto 0);
|
|
write_xerc_enable : std_ulogic;
|
|
write_xerc_data : xer_common_t;
|
|
end record;
|
|
constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
|
|
write_xerc_data => xerc_init,
|
|
write_cr_mask => (others => '0'),
|
|
write_cr_data => (others => '0'));
|
|
|
|
end common;
|
|
|
|
package body common is
|
|
function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
|
|
begin
|
|
return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
|
|
end;
|
|
function fast_spr_num(spr: spr_num_t) return gspr_index_t is
|
|
variable n : integer range 0 to 31;
|
|
-- tmp variable introduced as workaround for VCS compilation
|
|
-- simulation was failing with subtype constraint mismatch error
|
|
-- see GitHub PR #173
|
|
variable tmp : std_ulogic_vector(4 downto 0);
|
|
begin
|
|
case spr is
|
|
when SPR_LR =>
|
|
n := 0;
|
|
when SPR_CTR =>
|
|
n:= 1;
|
|
when SPR_SRR0 =>
|
|
n := 2;
|
|
when SPR_SRR1 =>
|
|
n := 3;
|
|
when SPR_HSRR0 =>
|
|
n := 4;
|
|
when SPR_HSRR1 =>
|
|
n := 5;
|
|
when SPR_SPRG0 =>
|
|
n := 6;
|
|
when SPR_SPRG1 =>
|
|
n := 7;
|
|
when SPR_SPRG2 =>
|
|
n := 8;
|
|
when SPR_SPRG3 | SPR_SPRG3U =>
|
|
n := 9;
|
|
when SPR_HSPRG0 =>
|
|
n := 10;
|
|
when SPR_HSPRG1 =>
|
|
n := 11;
|
|
when SPR_XER =>
|
|
n := 12;
|
|
when SPR_TAR =>
|
|
n := 13;
|
|
when others =>
|
|
n := 0;
|
|
return "0000000";
|
|
end case;
|
|
tmp := std_ulogic_vector(to_unsigned(n, 5));
|
|
return "01" & tmp;
|
|
end;
|
|
|
|
function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
|
|
begin
|
|
return i(4 downto 0);
|
|
end;
|
|
|
|
function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
|
|
begin
|
|
return "00" & i;
|
|
end;
|
|
|
|
function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
|
|
begin
|
|
if s(5) = '1' then
|
|
return s;
|
|
else
|
|
return gpr_to_gspr(g);
|
|
end if;
|
|
end;
|
|
|
|
function is_fast_spr(s: gspr_index_t) return std_ulogic is
|
|
begin
|
|
return s(5);
|
|
end;
|
|
|
|
function fpr_to_gspr(f: fpr_index_t) return gspr_index_t is
|
|
begin
|
|
return "10" & f;
|
|
end;
|
|
end common;
|