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24 lines
638 B
Python
24 lines
638 B
Python
from pathlib import Path
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from vunit import VUnit
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ROOT = Path(__file__).parent
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PRJ = VUnit.from_argv()
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PRJ.add_osvvm()
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PRJ.add_library("lib").add_source_files([
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ROOT / "litedram" / "extras" / "*.vhdl",
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ROOT / "litedram" / "generated" / "sim" / "*.vhdl"
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] + [
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src_file
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for src_file in ROOT.glob("*.vhdl")
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# Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
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if not any(exclude in str(src_file) for exclude in ["xilinx-mult", "foreign_random", "nonrandom"])
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])
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PRJ.add_library("unisim").add_source_files(ROOT / "sim-unisim" / "*.vhdl")
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PRJ.set_sim_option("disable_ieee_warnings", True)
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PRJ.main()
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