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501b6daf9b
The carry is currently internal to execute1. We don't handle any of the other XER fields. This creates type called "xer_common_t" that contains the commonly used XER bits (CA, CA32, SO, OV, OV32). The value is stored in the CR file (though it could be a separate module). The rest of the bits will be implemented as a separate SPR and the two parts reconciled in mfspr/mtspr in latter commits. We always read XER in decode2 (there is little point not to) and send it down all pipeline branches as it will be needed in writeback for all type of instructions when CR0:SO needs to be updated (such forms exist for all pipeline branches even if we don't yet implement them). To avoid having to track XER hazards, we forward it back in EX1. This assumes that other pipeline branches that can modify it (mult and div) are running single issue for now. One additional hazard to beware of is an XER:SO modifying instruction in EX1 followed immediately by a store conditional. Due to our writeback latency, the store will go down the LSU with the previous XER value, thus the stcx. will set CR0:SO using an obsolete SO value. I doubt there exist any code relying on this behaviour being correct but we should account for it regardless, possibly by ensuring that stcx. remain single issue initially, or later by adding some minimal tracking or moving the LSU into the same pipeline as execute. Missing some obscure XER affecting instructions like addex or mcrxrx. [paulus@ozlabs.org - fix CA32 and OV32 for OP_ADD, fix order of arguments to set_ov] Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
80 lines
1.9 KiB
VHDL
80 lines
1.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.helpers.all;
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-- 2 cycle LSU
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-- We calculate the address in the first cycle
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entity loadstore1 is
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port (
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clk : in std_ulogic;
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l_in : in Decode2ToLoadstore1Type;
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l_out : out Loadstore1ToDcacheType
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);
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end loadstore1;
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architecture behave of loadstore1 is
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signal r, rin : Loadstore1ToDcacheType;
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signal lsu_sum : std_ulogic_vector(63 downto 0);
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begin
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-- Calculate the address in the first cycle
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lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0');
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loadstore1_0: process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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end if;
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end process;
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loadstore1_1: process(all)
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variable v : Loadstore1ToDcacheType;
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begin
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v := r;
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v.valid := l_in.valid;
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v.load := l_in.load;
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v.data := l_in.data;
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v.write_reg := l_in.write_reg;
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v.length := l_in.length;
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v.byte_reverse := l_in.byte_reverse;
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v.sign_extend := l_in.sign_extend;
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v.update := l_in.update;
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v.update_reg := l_in.update_reg;
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v.xerc := l_in.xerc;
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-- XXX Temporary hack. Mark the op as non-cachable if the address
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-- is the form 0xc-------
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--
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-- This will have to be replaced by a combination of implementing the
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-- proper HV CI load/store instructions and having an MMU to get the I
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-- bit otherwise.
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if lsu_sum(31 downto 28) = "1100" then
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v.nc := '1';
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else
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v.nc := '0';
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end if;
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-- XXX Do length_to_sel here ?
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-- byte reverse stores in the first cycle
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if v.load = '0' and l_in.byte_reverse = '1' then
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v.data := byte_reverse(l_in.data, to_integer(unsigned(l_in.length)));
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end if;
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v.addr := lsu_sum;
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-- Update registers
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rin <= v;
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-- Update outputs
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l_out <= r;
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end process;
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end;
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