Anton Blanchard efb387b0d2 makefile: Add some verilator micropython tests ...

These are the same micropython tests we use against the ghdl
simulation.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

2021-08-14 19:36:29 +10:00

..

fmt_log

decode: Add a facility field to the instruction decode tables

2021-01-15 12:40:09 +11:00

mw_debug

core_debug: Add an address trigger to stop logging at a given address

2021-01-15 12:40:09 +11:00

bin2hex.py

bin2hex: Make sure to generate little endian files

2020-06-02 19:56:08 +10:00

dependencies.py

uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl

2020-06-24 09:53:46 +10:00

gen_icache_tb.py

icache_tb: Improve test and include test file

2019-10-18 16:41:05 +11:00

run_test_console.sh

Add test cases for new exceptions and supervisor state

2020-04-01 12:02:33 +11:00

run_test.sh

Dump CTR, LR and CR on sim termination, and update our tests

2020-01-11 11:09:38 +11:00

test_micropython_long.py

Update micropython

2020-01-19 21:36:38 +11:00

test_micropython_verilator_long.py

makefile: Add some verilator micropython tests

2021-08-14 19:36:29 +10:00

test_micropython_verilator.py

makefile: Add some verilator micropython tests

2021-08-14 19:36:29 +10:00

test_micropython.py

Update micropython

2020-01-19 21:36:38 +11:00

vhdltags

Add VHDL TAGS

2020-04-23 15:00:37 +10:00