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https://github.com/antonblanchard/microwatt.git
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ca4eb46aea
This makes the 64-bit wishbone buses have the address expressed in units of doublewords (64 bits), and similarly for the 32-bit buses the address is in units of words (32 bits). This is to comply with the wishbone spec. Previously the addresses on the wishbone buses were in units of bytes regardless of the bus data width, which is not correct and caused problems with interfacing with externally-generated logic. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
338 lines
10 KiB
VHDL
338 lines
10 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity dram_tb is
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generic (
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DRAM_INIT_FILE : string := "";
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DRAM_INIT_SIZE : natural := 0
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);
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end dram_tb;
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architecture behave of dram_tb is
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signal clk, rst: std_logic;
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signal clk_in, soc_rst : std_ulogic;
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-- testbench signals
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constant clk_period : time := 10 ns;
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-- Sim DRAM
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signal wb_in : wishbone_master_out;
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signal wb_out : wishbone_slave_out;
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signal wb_ctrl_in : wb_io_master_out;
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subtype addr_t is std_ulogic_vector(wb_in.adr'left downto 0);
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subtype data_t is std_ulogic_vector(wb_in.dat'left downto 0);
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subtype sel_t is std_ulogic_vector(wb_in.sel'left downto 0);
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-- Counter for acks
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signal acks : integer := 0;
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signal reset_acks : std_ulogic;
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-- Read data fifo
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signal rd_ready : std_ulogic := '0';
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signal rd_valid : std_ulogic;
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signal rd_data : data_t;
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begin
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dram: entity work.litedram_wrapper
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generic map(
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DRAM_ABITS => 24,
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DRAM_ALINES => 1,
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DRAM_DLINES => 16,
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DRAM_PORT_WIDTH => 128,
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PAYLOAD_FILE => DRAM_INIT_FILE,
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PAYLOAD_SIZE => DRAM_INIT_SIZE
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)
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port map(
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clk_in => clk_in,
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rst => rst,
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system_clk => clk,
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system_reset => soc_rst,
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core_alt_reset => open,
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pll_locked => open,
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wb_in => wb_in,
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wb_out => wb_out,
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wb_ctrl_in => wb_ctrl_in,
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wb_ctrl_out => open,
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wb_ctrl_is_csr => '0',
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wb_ctrl_is_init => '0',
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init_done => open,
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init_error => open,
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ddram_a => open,
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ddram_ba => open,
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ddram_ras_n => open,
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ddram_cas_n => open,
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ddram_we_n => open,
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ddram_cs_n => open,
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ddram_dm => open,
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ddram_dq => open,
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ddram_dqs_p => open,
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ddram_dqs_n => open,
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ddram_clk_p => open,
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ddram_clk_n => open,
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ddram_cke => open,
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ddram_odt => open,
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ddram_reset_n => open
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);
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clk_process: process
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begin
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clk_in <= '0';
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wait for clk_period/2;
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clk_in <= '1';
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wait for clk_period/2;
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end process;
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rst_process: process
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begin
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rst <= '1';
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wait for 10*clk_period;
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rst <= '0';
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wait;
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end process;
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wb_ctrl_in.cyc <= '0';
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wb_ctrl_in.stb <= '0';
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-- Read data receive queue
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data_queue: entity work.sync_fifo
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generic map (
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DEPTH => 16,
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WIDTH => rd_data'length
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)
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port map (
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clk => clk,
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reset => soc_rst or reset_acks,
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rd_ready => rd_ready,
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rd_valid => rd_valid,
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rd_data => rd_data,
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wr_ready => open,
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wr_valid => wb_out.ack,
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wr_data => wb_out.dat
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);
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recv_acks: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' or reset_acks = '1' then
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acks <= 0;
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elsif wb_out.ack = '1' then
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acks <= acks + 1;
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-- report "WB ACK ! DATA=" & to_hstring(wb_out.dat);
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end if;
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end if;
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end process;
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sim: process
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procedure wb_write(addr: addr_t; data: data_t; sel: sel_t) is
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begin
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wb_in.adr <= addr;
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wb_in.sel <= sel;
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wb_in.dat <= data;
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wb_in.we <= '1';
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wb_in.stb <= '1';
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wb_in.cyc <= '1';
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loop
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wait until rising_edge(clk);
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if wb_out.stall = '0' then
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wb_in.stb <= '0';
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exit;
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end if;
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end loop;
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end procedure;
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procedure wb_read(addr: addr_t) is
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begin
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wb_in.adr <= addr;
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wb_in.sel <= x"ff";
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wb_in.we <= '0';
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wb_in.stb <= '1';
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wb_in.cyc <= '1';
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loop
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wait until rising_edge(clk);
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if wb_out.stall = '0' then
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wb_in.stb <= '0';
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exit;
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end if;
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end loop;
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end procedure;
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procedure wait_acks(count: integer) is
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begin
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wait until acks = count;
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wait until rising_edge(clk);
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end procedure;
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procedure clr_acks is
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begin
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reset_acks <= '1';
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wait until rising_edge(clk);
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reset_acks <= '0';
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end procedure;
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procedure read_data(data: out data_t) is
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begin
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assert rd_valid = '1' report "No data to read" severity failure;
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rd_ready <= '1';
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wait until rising_edge(clk);
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rd_ready <= '0';
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data := rd_data;
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end procedure;
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function add_off(a: addr_t; off: integer) return addr_t is
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begin
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return addr_t(unsigned(a) + off);
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end function;
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function make_pattern(num : integer) return data_t is
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variable r : data_t;
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variable t,b : integer;
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begin
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for i in 0 to (data_t'length/8)-1 loop
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t := (i+1)*8-1;
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b := i*8;
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r(t downto b) := std_ulogic_vector(to_unsigned(num+1, 8));
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end loop;
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return r;
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end function;
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procedure check_data(p: data_t) is
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variable d : data_t;
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begin
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read_data(d);
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assert d = p report "bad data, want " & to_hstring(p) &
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" got " & to_hstring(d) severity failure;
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end procedure;
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variable a : addr_t := (others => '0');
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variable d : data_t := (others => '0');
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variable d1 : data_t := (others => '0');
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begin
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reset_acks <= '0';
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rst <= '1';
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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rst <= '0';
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wait until rising_edge(clk_in);
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wait until soc_rst = '0';
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wait until rising_edge(clk);
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report "Simple write miss...";
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clr_acks;
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wb_write(a, x"0123456789abcdef", x"ff");
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wait_acks(1);
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report "Simple read miss...";
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clr_acks;
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wb_read(a);
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wait_acks(1);
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read_data(d);
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assert d = x"0123456789abcdef" report "bad data, got " & to_hstring(d) severity failure;
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report "Simple read hit...";
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clr_acks;
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wb_read(a);
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wait_acks(1);
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read_data(d);
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assert d = x"0123456789abcdef" report "bad data, got " & to_hstring(d) severity failure;
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report "Back to back 4 stores 4 reads on hit...";
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clr_acks;
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for i in 0 to 3 loop
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wb_write(add_off(a, i), make_pattern(i), x"ff");
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end loop;
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for i in 0 to 3 loop
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wb_read(add_off(a, i));
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end loop;
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wait_acks(8);
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for i in 0 to 7 loop
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if i < 4 then
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read_data(d);
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else
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check_data(make_pattern(i-4));
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end if;
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end loop;
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report "Back to back 4 stores 4 reads on miss...";
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a(10) := '1';
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clr_acks;
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for i in 0 to 3 loop
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wb_write(add_off(a, i), make_pattern(i), x"ff");
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end loop;
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for i in 0 to 3 loop
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wb_read(add_off(a, i));
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end loop;
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wait_acks(8);
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for i in 0 to 7 loop
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if i < 4 then
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read_data(d);
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else
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check_data(make_pattern(i-4));
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end if;
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end loop;
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report "Back to back interleaved 4 stores 4 reads on hit...";
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a(10) := '1';
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clr_acks;
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for i in 0 to 3 loop
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wb_write(add_off(a, i), make_pattern(i), x"ff");
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wb_read(add_off(a, i));
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end loop;
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wait_acks(8);
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for i in 0 to 3 loop
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read_data(d);
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check_data(make_pattern(i));
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end loop;
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report "Pre-fill a line";
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a(11) := '1';
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clr_acks;
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wb_write(add_off(a, 0), x"1111111100000000", x"ff");
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wb_write(add_off(a, 1), x"3333333322222222", x"ff");
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wb_write(add_off(a, 2), x"5555555544444444", x"ff");
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wb_write(add_off(a, 3), x"7777777766666666", x"ff");
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wb_write(add_off(a, 4), x"9999999988888888", x"ff");
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wb_write(add_off(a, 5), x"bbbbbbbbaaaaaaaa", x"ff");
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wb_write(add_off(a, 6), x"ddddddddcccccccc", x"ff");
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wb_write(add_off(a, 7), x"ffffffffeeeeeeee", x"ff");
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wb_write(add_off(a, 8), x"1111111100000000", x"ff");
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wb_write(add_off(a, 9), x"3333333322222222", x"ff");
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wb_write(add_off(a, 10), x"5555555544444444", x"ff");
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wb_write(add_off(a, 11), x"7777777766666666", x"ff");
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wb_write(add_off(a, 12), x"9999999988888888", x"ff");
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wb_write(add_off(a, 13), x"bbbbbbbbaaaaaaaa", x"ff");
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wb_write(add_off(a, 14), x"ddddddddcccccccc", x"ff");
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wb_write(add_off(a, 15), x"ffffffffeeeeeeee", x"ff");
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wait_acks(16);
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report "Scattered from middle of line...";
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clr_acks;
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wb_read(add_off(a, 3));
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wb_read(add_off(a, 4));
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wb_read(add_off(a, 0));
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wb_read(add_off(a, 2));
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wait_acks(4);
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read_data(d);
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assert d = x"7777777766666666" report "bad data (24), got " & to_hstring(d) severity failure;
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read_data(d);
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assert d = x"9999999988888888" report "bad data (32), got " & to_hstring(d) severity failure;
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read_data(d);
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assert d = x"1111111100000000" report "bad data (0), got " & to_hstring(d) severity failure;
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read_data(d);
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assert d = x"5555555544444444" report "bad data (16), got " & to_hstring(d) severity failure;
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std.env.finish;
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end process;
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end architecture;
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