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ca4eb46aea
This makes the 64-bit wishbone buses have the address expressed in units of doublewords (64 bits), and similarly for the 32-bit buses the address is in units of words (32 bits). This is to comply with the wishbone spec. Previously the addresses on the wishbone buses were in units of bytes regardless of the bus data width, which is not correct and caused problems with interfacing with externally-generated logic. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
59 lines
2.3 KiB
VHDL
59 lines
2.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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package wishbone_types is
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--
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-- Main CPU bus. 32-bit address, 64-bit data,
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-- so the wishbone address is in units of 8 bytes.
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--
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constant wishbone_addr_bits : integer := 29;
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constant wishbone_data_bits : integer := 64;
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constant wishbone_sel_bits : integer := wishbone_data_bits/8;
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constant wishbone_log2_width : integer := 3;
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subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0);
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subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0);
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subtype wishbone_sel_type is std_ulogic_vector(wishbone_sel_bits-1 downto 0);
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type wishbone_master_out is record
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adr : wishbone_addr_type;
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dat : wishbone_data_type;
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sel : wishbone_sel_type;
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cyc : std_ulogic;
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stb : std_ulogic;
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we : std_ulogic;
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end record;
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constant wishbone_master_out_init : wishbone_master_out := (adr => (others => '0'), dat => (others => '0'), cyc => '0', stb => '0', sel => (others => '0'), we => '0');
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type wishbone_slave_out is record
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dat : wishbone_data_type;
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ack : std_ulogic;
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stall : std_ulogic;
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end record;
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constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', stall => '0', others => (others => '0'));
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type wishbone_master_out_vector is array (natural range <>) of wishbone_master_out;
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type wishbone_slave_out_vector is array (natural range <>) of wishbone_slave_out;
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--
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-- IO Bus to a device, 30-bit address, 32-bits data
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--
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type wb_io_master_out is record
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adr : std_ulogic_vector(29 downto 0);
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dat : std_ulogic_vector(31 downto 0);
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sel : std_ulogic_vector(3 downto 0);
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cyc : std_ulogic;
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stb : std_ulogic;
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we : std_ulogic;
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end record;
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constant wb_io_master_out_init : wb_io_master_out := (adr => (others => '0'), dat => (others => '0'),
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sel => "0000", cyc => '0', stb => '0', we => '0');
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type wb_io_slave_out is record
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dat : std_ulogic_vector(31 downto 0);
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ack : std_ulogic;
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stall : std_ulogic;
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end record;
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constant wb_io_slave_out_init : wb_io_slave_out := (ack => '0', stall => '0', others => (others => '0'));
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end package wishbone_types;
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