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https://github.com/antonblanchard/microwatt.git
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bf7def5503
Currently, when not using litedram, the top level still has to hook up "dummy" wishbones to the main dram and control dram busses coming out of the SoC and provide ack signals. Instead, make the SoC generate the acks internally when not using litedram and use defaults to make the wiring entirely optional. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
98 lines
2.5 KiB
VHDL
98 lines
2.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity core_flash_tb is
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end core_flash_tb;
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architecture behave of core_flash_tb is
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signal clk, rst: std_logic;
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-- testbench signals
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constant clk_period : time := 10 ns;
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-- SPI
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signal spi_sck : std_ulogic;
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signal spi_cs_n : std_ulogic := '1';
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signal spi_sdat_o : std_ulogic_vector(3 downto 0);
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signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
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signal spi_sdat_i : std_ulogic_vector(3 downto 0);
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signal fl_hold_n : std_logic;
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signal fl_wp_n : std_logic;
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signal fl_mosi : std_logic;
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signal fl_miso : std_logic;
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begin
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soc0: entity work.soc
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generic map(
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SIM => true,
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MEMORY_SIZE => (384*1024),
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RAM_INIT_FILE => "main_ram.bin",
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CLK_FREQ => 100000000,
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HAS_SPI_FLASH => true,
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SPI_FLASH_DLINES => 4,
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SPI_FLASH_OFFSET => 0
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)
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port map(
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rst => rst,
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system_clk => clk,
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spi_flash_sck => spi_sck,
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spi_flash_cs_n => spi_cs_n,
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spi_flash_sdat_o => spi_sdat_o,
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spi_flash_sdat_oe => spi_sdat_oe,
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spi_flash_sdat_i => spi_sdat_i
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);
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flash: entity work.s25fl128s
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generic map (
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TimingModel => "S25FL128SAGNFI000_R_30pF",
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LongTimming => false,
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tdevice_PU => 10 ns,
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tdevice_PP256 => 100 ns,
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tdevice_PP512 => 100 ns,
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tdevice_WRR => 100 ns
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)
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port map(
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SCK => spi_sck,
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SI => fl_mosi,
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CSNeg => spi_cs_n,
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HOLDNeg => fl_hold_n,
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WPNeg => fl_wp_n,
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RSTNeg => '1',
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SO => fl_miso
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);
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fl_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
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fl_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
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fl_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
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fl_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else '1' when spi_sdat_oe(0) = '1' else 'Z';
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spi_sdat_i(0) <= fl_mosi;
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spi_sdat_i(1) <= fl_miso;
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spi_sdat_i(2) <= fl_wp_n;
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spi_sdat_i(3) <= fl_hold_n;
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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rst_process: process
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begin
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rst <= '1';
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wait for 10*clk_period;
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rst <= '0';
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wait;
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end process;
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jtag: entity work.sim_jtag;
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end;
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