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https://github.com/antonblanchard/microwatt.git
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49a4d9f67a
This logs 256 bits of data per cycle to a ring buffer in BRAM. The data collected can be read out through 2 new SPRs or through the debug interface. The new SPRs are LOG_ADDR (724) and LOG_DATA (725). LOG_ADDR contains the buffer write pointer in the upper 32 bits (in units of entries, i.e. 32 bytes) and the read pointer in the lower 32 bits (in units of doublewords, i.e. 8 bytes). Reading LOG_DATA gives the doubleword from the buffer at the read pointer and increments the read pointer. Setting bit 31 of LOG_ADDR inhibits the trace log system from writing to the log buffer, so the contents are stable and can be read. There are two new debug addresses which function similarly to the LOG_ADDR and LOG_DATA SPRs. The log is frozen while either or both of the LOG_ADDR SPR bit 31 or the debug LOG_ADDR register bit 31 are set. The buffer defaults to 2048 entries, i.e. 64kB. The size is set by the LOG_LENGTH generic on the core_debug module. Software can determine the length of the buffer because the length is ORed into the buffer write pointer in the upper 32 bits of LOG_ADDR. Hence the length of the buffer can be calculated as 1 << (31 - clz(LOG_ADDR)). There is a program to format the log entries in a somewhat readable fashion in scripts/fmt_log/fmt_log.c. The log_entry struct in that file describes the layout of the bits in the log entries. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
105 lines
2.7 KiB
VHDL
105 lines
2.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity cr_file is
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generic (
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SIM : boolean := false
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);
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port(
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clk : in std_logic;
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d_in : in Decode2ToCrFileType;
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d_out : out CrFileToDecode2Type;
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w_in : in WritebackToCrFileType;
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-- debug
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sim_dump : in std_ulogic;
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log_out : out std_ulogic_vector(12 downto 0)
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);
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end entity cr_file;
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architecture behaviour of cr_file is
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signal crs : std_ulogic_vector(31 downto 0) := (others => '0');
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signal crs_updated : std_ulogic_vector(31 downto 0);
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signal xerc : xer_common_t := xerc_init;
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signal xerc_updated : xer_common_t;
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signal log_data : std_ulogic_vector(12 downto 0);
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begin
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cr_create_0: process(all)
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variable hi, lo : integer := 0;
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variable cr_tmp : std_ulogic_vector(31 downto 0) := (others => '0');
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begin
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cr_tmp := crs;
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for i in 0 to 7 loop
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if w_in.write_cr_mask(i) = '1' then
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lo := i*4;
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hi := lo + 3;
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cr_tmp(hi downto lo) := w_in.write_cr_data(hi downto lo);
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end if;
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end loop;
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crs_updated <= cr_tmp;
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if w_in.write_xerc_enable = '1' then
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xerc_updated <= w_in.write_xerc_data;
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else
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xerc_updated <= xerc;
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end if;
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end process;
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-- synchronous writes
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cr_write_0: process(clk)
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begin
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if rising_edge(clk) then
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if w_in.write_cr_enable = '1' then
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report "Writing " & to_hstring(w_in.write_cr_data) & " to CR mask " & to_hstring(w_in.write_cr_mask);
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crs <= crs_updated;
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end if;
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if w_in.write_xerc_enable = '1' then
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report "Writing XERC";
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xerc <= xerc_updated;
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end if;
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end if;
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end process;
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-- asynchronous reads
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cr_read_0: process(all)
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begin
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-- just return the entire CR to make mfcrf easier for now
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if d_in.read = '1' then
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report "Reading CR " & to_hstring(crs_updated);
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end if;
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d_out.read_cr_data <= crs_updated;
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d_out.read_xerc_data <= xerc_updated;
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end process;
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sim_dump_test: if SIM generate
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dump_cr: process(all)
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begin
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if sim_dump = '1' then
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report "CR 00000000" & to_hstring(crs);
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assert false report "end of test" severity failure;
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end if;
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end process;
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end generate;
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cr_log: process(clk)
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begin
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if rising_edge(clk) then
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log_data <= w_in.write_cr_enable &
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w_in.write_cr_data(31 downto 28) &
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w_in.write_cr_mask;
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end if;
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end process;
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log_out <= log_data;
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end architecture behaviour;
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