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467630573c
Right now our test cases fold the SPRs into the GPRs. That makes debugging fails more difficult than it needs to be, so print out the CTR, LR and CR. We still need to print the XER, but that is in two spots in microwatt and will take some more work. This also adds many instructions to the tests that we have added lately including overflow instructions, CR logicals and mt/mfxer. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
92 lines
2.3 KiB
VHDL
92 lines
2.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity cr_file is
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generic (
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SIM : boolean := false
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);
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port(
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clk : in std_logic;
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d_in : in Decode2ToCrFileType;
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d_out : out CrFileToDecode2Type;
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w_in : in WritebackToCrFileType;
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-- debug
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sim_dump : in std_ulogic
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);
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end entity cr_file;
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architecture behaviour of cr_file is
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signal crs : std_ulogic_vector(31 downto 0) := (others => '0');
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signal crs_updated : std_ulogic_vector(31 downto 0);
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signal xerc : xer_common_t := xerc_init;
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signal xerc_updated : xer_common_t;
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begin
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cr_create_0: process(all)
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variable hi, lo : integer := 0;
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variable cr_tmp : std_ulogic_vector(31 downto 0) := (others => '0');
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begin
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cr_tmp := crs;
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for i in 0 to 7 loop
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if w_in.write_cr_mask(i) = '1' then
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lo := i*4;
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hi := lo + 3;
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cr_tmp(hi downto lo) := w_in.write_cr_data(hi downto lo);
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end if;
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end loop;
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crs_updated <= cr_tmp;
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if w_in.write_xerc_enable = '1' then
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xerc_updated <= w_in.write_xerc_data;
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else
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xerc_updated <= xerc;
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end if;
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end process;
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-- synchronous writes
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cr_write_0: process(clk)
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begin
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if rising_edge(clk) then
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if w_in.write_cr_enable = '1' then
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report "Writing " & to_hstring(w_in.write_cr_data) & " to CR mask " & to_hstring(w_in.write_cr_mask);
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crs <= crs_updated;
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end if;
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if w_in.write_xerc_enable = '1' then
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report "Writing XERC";
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xerc <= xerc_updated;
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end if;
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end if;
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end process;
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-- asynchronous reads
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cr_read_0: process(all)
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begin
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-- just return the entire CR to make mfcrf easier for now
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if d_in.read = '1' then
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report "Reading CR " & to_hstring(crs_updated);
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end if;
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d_out.read_cr_data <= crs_updated;
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d_out.read_xerc_data <= xerc_updated;
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end process;
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sim_dump_test: if SIM generate
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dump_cr: process(all)
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begin
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if sim_dump = '1' then
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report "CR 00000000" & to_hstring(crs);
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assert false report "end of test" severity failure;
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end if;
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end process;
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end generate;
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end architecture behaviour;
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