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b14d982011
This enables back-to-back execution of integer instructions where the first instruction writes a GPR and the second reads the same GPR. This is done with a set of multiplexers at the start of execute1 which enable any of the three input operands to be taken from the output of execute1 (i.e. r.e.write_data) rather than the input from decode2 (i.e. e_in.read_data[123]). This also requires changes to the hazard detection and handling. Decode2 generates a signal indicating that the GPR being written is available for bypass, which is true for instructions that are executed in execute1 (rather than loadstore1/dcache). The gpr_hazard module stores this "bypassable" bit, and if the same GPR needs to be read by a subsequent instruction, it outputs a "use_bypass" signal rather than generating a stall. The use_bypass signal is then latched at the output of decode2 and passed down to execute1 to control the input multiplexer. At the moment there is no bypass on the inputs to loadstore1, but that is OK because all load and store instructions are marked as single-issue. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
99 lines
3.0 KiB
VHDL
99 lines
3.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity gpr_hazard is
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generic (
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PIPELINE_DEPTH : natural := 2
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);
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port(
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clk : in std_ulogic;
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stall_in : in std_ulogic;
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gpr_write_valid_in : in std_ulogic;
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gpr_write_in : in std_ulogic_vector(5 downto 0);
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bypass_avail : in std_ulogic;
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gpr_read_valid_in : in std_ulogic;
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gpr_read_in : in std_ulogic_vector(5 downto 0);
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stall_out : out std_ulogic;
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use_bypass : out std_ulogic
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);
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end entity gpr_hazard;
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architecture behaviour of gpr_hazard is
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type pipeline_entry_type is record
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valid : std_ulogic;
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bypass : std_ulogic;
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gpr : std_ulogic_vector(5 downto 0);
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end record;
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constant pipeline_entry_init : pipeline_entry_type := (valid => '0', bypass => '0', gpr => (others => '0'));
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type pipeline_t is array(0 to PIPELINE_DEPTH-1) of pipeline_entry_type;
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constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
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signal r, rin : pipeline_t := pipeline_t_init;
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begin
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gpr_hazard0: process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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end if;
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end process;
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gpr_hazard1: process(all)
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variable v : pipeline_t;
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begin
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v := r;
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stall_out <= '0';
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use_bypass <= '0';
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if gpr_read_valid_in = '1' then
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if r(0).valid = '1' and r(0).gpr = gpr_read_in then
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if r(0).bypass = '1' and stall_in = '0' then
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use_bypass <= '1';
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else
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stall_out <= '1';
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end if;
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end if;
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loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
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if r(i).valid = '1' and r(i).gpr = gpr_read_in then
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if r(i).bypass = '1' then
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use_bypass <= '1';
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else
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stall_out <= '1';
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end if;
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end if;
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end loop;
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end if;
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if stall_in = '0' then
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v(0).valid := gpr_write_valid_in;
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v(0).bypass := bypass_avail;
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v(0).gpr := gpr_write_in;
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loop_1: for i in 1 to PIPELINE_DEPTH-1 loop
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-- propagate to next slot
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v(i).valid := r(i-1).valid;
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v(i).bypass := r(i-1).bypass;
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v(i).gpr := r(i-1).gpr;
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end loop;
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else
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-- stage 0 stalled, so stage 1 becomes empty
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loop_1b: for i in 1 to PIPELINE_DEPTH-1 loop
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-- propagate to next slot
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if i = 1 then
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v(i).valid := '0';
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else
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v(i).valid := r(i-1).valid;
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v(i).bypass := r(i-1).bypass;
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v(i).gpr := r(i-1).gpr;
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end if;
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end loop;
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end if;
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-- update registers
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rin <= v;
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end process;
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end;
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