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Benjamin Herrenschmidt 8e0389b973 ram: Rework main RAM interface
This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-10-30 13:18:58 +11:00

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#!/bin/bash
if [ $# -ne 1 ]; then
echo "Usage: run_test.sh <test>"
exit 1
fi
TEST=$1
TMPDIR=$(mktemp -d)
function finish {
rm -rf "$TMPDIR"
}
trap finish EXIT
MICROWATT_DIR=$PWD
Y=$(${MICROWATT_DIR}/scripts/hash.py tests/${TEST}.out)
cd $TMPDIR
cp ${MICROWATT_DIR}/tests/${TEST}.bin main_ram.bin
X=$( ${MICROWATT_DIR}/core_tb | ${MICROWATT_DIR}/scripts/hash.py )
if [ $X == $Y ]; then
echo "$TEST PASS"
else
echo "$TEST FAIL ********"
exit 1
fi