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d21ef5836d17e672751296eedb819a2b8884b0fd
antonblanchard.microwatt/fpga
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Benjamin Herrenschmidt d21ef5836d Pass wishbone record to bram memory module 
(And rename it to mw_soc_memory).

This makes soc.vhdl simpler and provides the same interface as
the simulated memory, which will help when sharing soc.vhdl
with sim later

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-10 16:57:47 +01:00
..
arty_a7-35.xdc
Merge pull request #20 from antonblanchard/reset-rework2
2019-09-08 16:34:10 +10:00
clk_gen_bypass.vhd
Rework SOC reset
2019-09-08 07:40:19 +10:00
clk_gen_mcmm.vhd
Cmod A7-35 support
2019-09-08 16:36:50 +10:00
clk_gen_plle2.vhd
Rework SOC reset
2019-09-08 07:40:19 +10:00
cmod_a7-35.xdc
Cmod A7-35 support
2019-09-08 16:36:50 +10:00
firmware.hex
Add a few more FPGA related files
2019-08-23 16:23:53 +10:00
hello_world.hex
Rebuild hello world assuming a 50MHz clock
2019-08-26 22:09:28 +10:00
LICENSE
Initial import of microwatt
2019-08-22 16:46:13 +10:00
mw_soc_memory.vhdl
Pass wishbone record to bram memory module
2019-09-10 16:57:47 +01:00
nexys_a7.xdc
Merge pull request #20 from antonblanchard/reset-rework2
2019-09-08 16:34:10 +10:00
nexys-video.xdc
Rename a few reset signals
2019-09-07 21:33:50 +10:00
nodivide.patch
Add a few more FPGA related files
2019-08-23 16:23:53 +10:00
pp_fifo.vhd
Initial import of microwatt
2019-08-22 16:46:13 +10:00
pp_soc_uart.vhd
Initial import of microwatt
2019-08-22 16:46:13 +10:00
pp_utilities.vhd
Initial import of microwatt
2019-08-22 16:46:13 +10:00
soc_reset_tb.vhdl
Rework SOC reset
2019-09-08 07:40:19 +10:00
soc_reset.vhdl
Rework SOC reset
2019-09-08 07:40:19 +10:00
soc.vhdl
Pass wishbone record to bram memory module
2019-09-10 16:57:47 +01:00
toplevel.vhdl
Split FPGA toplevel from soc
2019-09-10 16:50:49 +01:00