mirror of
https://github.com/antonblanchard/microwatt.git
synced 2026-01-13 15:18:09 +00:00
39d18d2738
With this, the divider is a unit that execute1 sends operands to and which sends its results back to execute1, which then send them to writeback. Execute1 now sends a stall signal when it gets a divide or modulus instruction until it gets a valid signal back from the divider. Divide and modulus instructions are no longer marked as single-issue. The data formatting step that used to be done in decode2 for div and mod instructions is now done in execute1. We also do the absolute value operation in that same cycle instead of taking an extra cycle inside the divider for signed operations with a negative operand. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
137 lines
4.2 KiB
Makefile
137 lines
4.2 KiB
Makefile
GHDL=ghdl
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GHDLFLAGS=--std=08 -Psim-unisim
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CFLAGS=-O2 -Wall
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all = core_tb soc_reset_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
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rotator_tb countzero_tb wishbone_bram_tb
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# XXX
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# loadstore_tb fetch_tb
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all: $(all)
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%.o : %.vhdl
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$(GHDL) -a $(GHDLFLAGS) $<
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common.o: decode_types.o
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control.o: gpr_hazard.o cr_hazard.o common.o
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sim_jtag.o: sim_jtag_socket.o
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core_tb.o: common.o wishbone_types.o core.o soc.o sim_jtag.o
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core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o loadstore1.o dcache.o writeback.o core_debug.o
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core_debug.o: common.o
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countzero.o:
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countzero_tb.o: common.o glibc_random.o countzero.o
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cr_file.o: common.o
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crhelpers.o: common.o
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decode1.o: common.o decode_types.o
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decode2.o: decode_types.o common.o helpers.o insn_helpers.o control.o
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decode_types.o:
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execute1.o: decode_types.o common.o helpers.o crhelpers.o insn_helpers.o ppc_fx_insns.o rotator.o logical.o countzero.o multiply.o divider.o
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fetch1.o: common.o
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fetch2.o: common.o wishbone_types.o
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glibc_random_helpers.o:
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glibc_random.o: glibc_random_helpers.o
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helpers.o:
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cache_ram.o:
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plru.o:
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plru_tb.o: plru.o
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utils.o:
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sim_bram.o: sim_bram_helpers.o utils.o
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wishbone_bram_wrapper.o: wishbone_types.o sim_bram.o utils.o
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wishbone_bram_tb.o: wishbone_bram_wrapper.o
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icache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o
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icache_tb.o: common.o wishbone_types.o icache.o wishbone_bram_wrapper.o
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dcache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o
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dcache_tb.o: common.o wishbone_types.o dcache.o wishbone_bram_wrapper.o
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insn_helpers.o:
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loadstore1.o: common.o helpers.o
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logical.o: decode_types.o
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multiply_tb.o: decode_types.o common.o glibc_random.o ppc_fx_insns.o multiply.o
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multiply.o: common.o decode_types.o
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divider_tb.o: decode_types.o common.o glibc_random.o ppc_fx_insns.o divider.o
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divider.o: common.o decode_types.o
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ppc_fx_insns.o: helpers.o
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register_file.o: common.o
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rotator.o: common.o
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rotator_tb.o: common.o glibc_random.o ppc_fx_insns.o insn_helpers.o rotator.o
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sim_console.o:
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sim_uart.o: wishbone_types.o sim_console.o
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soc.o: common.o wishbone_types.o core.o wishbone_arbiter.o sim_uart.o wishbone_bram_wrapper.o dmi_dtm_xilinx.o wishbone_debug_master.o
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wishbone_arbiter.o: wishbone_types.o
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wishbone_types.o:
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writeback.o: common.o crhelpers.o
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dmi_dtm_tb.o: dmi_dtm_xilinx.o wishbone_debug_master.o
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dmi_dtm_xilinx.o: wishbone_types.o sim-unisim/unisim_vcomponents.o
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wishbone_debug_master.o: wishbone_types.o
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UNISIM_BITS = sim-unisim/unisim_vcomponents.vhdl sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl
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sim-unisim/unisim_vcomponents.o: $(UNISIM_BITS)
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$(GHDL) -a $(GHDLFLAGS) --work=unisim --workdir=sim-unisim $^
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fpga/soc_reset_tb.o: fpga/soc_reset.o
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soc_reset_tb: fpga/soc_reset_tb.o fpga/soc_reset.o
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$(GHDL) -e $(GHDLFLAGS) soc_reset_tb
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core_tb: core_tb.o sim_bram_helpers_c.o sim_console_c.o sim_jtag_socket_c.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o -Wl,sim_console_c.o -Wl,sim_jtag_socket_c.o $@
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fetch_tb: fetch_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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icache_tb: icache_tb.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o $@
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dcache_tb: dcache_tb.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o $@
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plru_tb: plru_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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loadstore_tb: loadstore_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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multiply_tb: multiply_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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divider_tb: divider_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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rotator_tb: rotator_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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countzero_tb: countzero_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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simple_ram_tb: simple_ram_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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wishbone_bram_tb: sim_bram_helpers_c.o wishbone_bram_tb.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o $@
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dmi_dtm_tb: dmi_dtm_tb.o sim_bram_helpers_c.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o $@
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tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
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check: $(tests) test_micropython test_micropython_long
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check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long
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$(tests): core_tb
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@./scripts/run_test.sh $@
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test_micropython: core_tb
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@./scripts/test_micropython.py
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test_micropython_long: core_tb
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@./scripts/test_micropython_long.py
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clean:
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rm -f *.o work-*cf unisim-*cf $(all)
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rm -f sim-unisim/*.o sim-unisim/unisim-*cf
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distclean: clean
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rm -f *~ fpga/~
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