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https://github.com/antonblanchard/microwatt.git
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3510071d9a
This adds a second execute stage to the pipeline, in order to match up the length of the pipeline through loadstore and dcache with the length through execute1. This will ultimately enable us to get rid of the 1-cycle bubble that we currently have when issuing ALU instructions after one or more LSU instructions. Most ALU instructions execute in the first stage, except for count-zeroes and popcount instructions (which take two cycles and do some of their work in the second stage) and mfspr/mtspr to "slow" SPRs (TB, DEC, PVR, LOGA/LOGD, CFAR). Multiply and divide/mod instructions take several cycles but the instruction stays in the first stage (ex1) and ex1.busy is asserted until the operation is complete. There is currently a bypass from the first stage but not the second stage. Performance is down somewhat because of that and because this doesn't yet eliminate the bubble between LSU and ALU instructions. The forwarding of XER common bits has been changed somewhat because now there is another pipeline stage between ex1 and the committed state in cr_file. The simplest thing for now is to record the last value written and use that, unless there has been a flush, in which case the committed state (obtained via e_in.xerc) is used. Note that this fixes what was previously a benign bug in control.vhdl, where it was possible for control to forget an instructions dependency on a value from a previous instruction (a GPR or the CR) if this instruction writes the value and the instruction gets to the point where it could issue but is blocked by the busy signal from execute1. In that situation, control may incorrectly not indicate that a bypass should be used. That didn't matter previously because, for ALU and FPU instructions, there was only one previous instruction in flight and once the current instruction could issue, the previous instruction was completing and the correct value would be obtained from register_file or cr_file. For loadstore instructions there could be two being executed, but because there are no bypass paths, failing to indicate use of a bypass path is fine. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
120 lines
3.9 KiB
VHDL
120 lines
3.9 KiB
VHDL
library vunit_lib;
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context vunit_lib.vunit_context;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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entity countbits_tb is
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generic (runner_cfg : string := runner_cfg_default);
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end countbits_tb;
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architecture behave of countbits_tb is
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constant clk_period: time := 10 ns;
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signal rs: std_ulogic_vector(63 downto 0);
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signal is_32bit, count_right: std_ulogic := '0';
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signal res: std_ulogic_vector(63 downto 0);
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signal clk: std_ulogic;
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begin
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bitcounter_0: entity work.bit_counter
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port map (
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clk => clk,
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stall => '0',
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rs => rs,
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result => res,
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count_right => count_right,
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is_32bit => is_32bit,
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do_popcnt => '0',
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datalen => "0000"
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);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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stim_process: process
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variable r: std_ulogic_vector(63 downto 0);
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variable rnd : RandomPType;
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begin
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rnd.InitSeed(stim_process'path_name);
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test_runner_setup(runner, runner_cfg);
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while test_suite loop
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if run("Test with input = 0") then
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rs <= (others => '0');
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is_32bit <= '0';
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count_right <= '0';
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wait for clk_period;
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check_equal(res, 16#40#, result("for cntlzd"));
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count_right <= '1';
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wait for clk_period;
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check_equal(res, 16#40#, result("for cnttzd"));
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is_32bit <= '1';
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count_right <= '0';
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wait for clk_period;
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check_equal(res, 16#20#, result("for cntlzw"));
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count_right <= '1';
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wait for clk_period;
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check_equal(res, 16#20#, result("for cnttzw"));
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elsif run("Test cntlzd/w") then
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count_right <= '0';
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for j in 0 to 100 loop
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r := rnd.RandSlv(64);
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r(63) := '1';
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for i in 0 to 63 loop
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rs <= r;
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is_32bit <= '0';
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wait for clk_period;
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check_equal(res, i, result("for cntlzd " & to_hstring(rs)));
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rs <= r(31 downto 0) & r(63 downto 32);
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is_32bit <= '1';
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wait for clk_period;
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if i < 32 then
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check_equal(res, i, result("for cntlzw " & to_hstring(rs)));
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else
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check_equal(res, 32, result("for cntlzw " & to_hstring(rs)));
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end if;
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r := '0' & r(63 downto 1);
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end loop;
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end loop;
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elsif run("Test cnttzd/w") then
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count_right <= '1';
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for j in 0 to 100 loop
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r := rnd.RandSlv(64);
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r(0) := '1';
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for i in 0 to 63 loop
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rs <= r;
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is_32bit <= '0';
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wait for clk_period;
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check_equal(res, i, result("for cnttzd " & to_hstring(rs)));
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is_32bit <= '1';
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wait for clk_period;
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if i < 32 then
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check_equal(res, i, result("for cnttzw " & to_hstring(rs)));
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else
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check_equal(res, 32, result("for cnttzw " & to_hstring(rs)));
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end if;
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r := r(62 downto 0) & '0';
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end loop;
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end loop;
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end if;
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end loop;
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test_runner_cleanup(runner);
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end process;
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end behave;
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