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8901e84d8d
Parameters are based on https://github.com/gregdavill/OrangeCrab-test-sw/blob/main/hw/OrangeCrab-bitstream.py and litex-boards orangecrab.py rtt_nom and cmd_delay are overridden for OrangeCrab, we do the same here. Generated with litedram and litex 62abf9c ("litedram_gen: Add block_until_ready port parameter to control blocking behaviour.") add2746a ("tools/litex_cli: Rename wb to bus.") Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
40 lines
1.5 KiB
YAML
40 lines
1.5 KiB
YAML
# Matt Johnston 2021
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# Based on parameters from Greg Davill's Orangecrab-test-sw
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{
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"cpu": "None", # CPU type (ex vexriscv, serv, None)
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"device": "LFE5U-85F-8MG285C",
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"memtype": "DDR3", # DRAM type
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"sdram_module": "MT41K256M16", # SDRAM modules of the board or SO-DIMM
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"sdram_module_nb": 2, # Number of byte groups
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"sdram_rank_nb": 1, # Number of ranks
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"sdram_phy": "ECP5DDRPHY", # Type of FPGA PHY
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# Electrical ---------------------------------------------------------------
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"rtt_nom": "disabled", # Nominal termination. ("disabled" from orangecrab)
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"rtt_wr": "60ohm", # Write termination. (Default)
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"ron": "34ohm", # Output driver impedance. (Default)
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# Frequency ----------------------------------------------------------------
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"init_clk_freq": 24e6,
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"input_clk_freq": 48e6, # Input clock frequency
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"sys_clk_freq": 48e6, # System clock frequency (DDR_clk = 4 x sys_clk)
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# 0 if freq >64e6 else 100. https://github.com/enjoy-digital/litedram/issues/130
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"cmd_delay": 100,
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# Core ---------------------------------------------------------------------
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"cmd_buffer_depth": 16, # Depth of the command buffer
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"dm_swap": true,
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# User Ports ---------------------------------------------------------------
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"user_ports": {
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"native_0": {
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"type": "native",
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"block_until_ready": False,
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},
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},
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}
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