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https://github.com/antonblanchard/microwatt.git
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Instead of doing mfctr, mflr, mftb, mtctr, mtlr as separate ops, just pass down mfspr and mtspr ops with the spr number and let execute1 decode which SPR we're addressing. This will help reduce the number of instruction bits decode1 needs to look at. In fact we now pass down the whole instruction from decode2 to execute1. We will need more bits of the instruction in future, and the tools should just optimize away any that we don't end up using. Since the 'aa' bit was just a copy of an instruction bit, we can now remove it from the record. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
139 lines
5.4 KiB
VHDL
139 lines
5.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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package decode_types is
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type ppc_insn_t is (PPC_ILLEGAL, PPC_ADD, PPC_ADDC, PPC_ADDE,
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PPC_ADDEX, PPC_ADDI, PPC_ADDIC, PPC_ADDIC_RC, PPC_ADDIS,
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PPC_ADDME, PPC_ADDPCIS, PPC_ADDZE, PPC_AND, PPC_ANDC,
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PPC_ANDI_RC, PPC_ANDIS_RC, PPC_ATTN, PPC_B, PPC_BC,
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PPC_BCCTR, PPC_BCLR, PPC_BCTAR, PPC_BPERM,
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PPC_CMP, PPC_CMPB, PPC_CMPEQB, PPC_CMPI, PPC_CMPL, PPC_CMPLI,
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PPC_CMPRB, PPC_CNTLZD, PPC_CNTLZW, PPC_CNTTZD, PPC_CNTTZW,
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PPC_CRAND, PPC_CRANDC, PPC_CREQV, PPC_CRNAND, PPC_CRNOR,
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PPC_CROR, PPC_CRORC, PPC_CRXOR, PPC_DARN, PPC_DCBF, PPC_DCBST,
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PPC_DCBT, PPC_DCBTST, PPC_DCBZ, PPC_DIV,
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PPC_EQV, PPC_EXTSB, PPC_EXTSH, PPC_EXTSW,
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PPC_EXTSWSLI, PPC_ICBI, PPC_ICBT, PPC_ISEL, PPC_ISYNC,
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PPC_LBARX, PPC_LBZ, PPC_LBZU, PPC_LBZUX, PPC_LBZX, PPC_LD,
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PPC_LDARX, PPC_LDBRX, PPC_LDU, PPC_LDUX, PPC_LDX, PPC_LHA,
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PPC_LHARX, PPC_LHAU, PPC_LHAUX, PPC_LHAX, PPC_LHBRX, PPC_LHZ,
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PPC_LHZU, PPC_LHZUX, PPC_LHZX, PPC_LWA, PPC_LWARX, PPC_LWAUX,
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PPC_LWAX, PPC_LWBRX, PPC_LWZ, PPC_LWZU, PPC_LWZUX, PPC_LWZX,
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PPC_MADDHD, PPC_MADDHDU, PPC_MADDLD, PPC_MCRF, PPC_MCRXR,
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PPC_MCRXRX, PPC_MFCR, PPC_MFOCRF, PPC_MFSPR, PPC_MFTB,
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PPC_MOD, PPC_MTCRF,
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PPC_MFCTR, PPC_MTCTR, PPC_MFLR, PPC_MTLR, PPC_MTOCRF,
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PPC_MTSPR, PPC_MULHD, PPC_MULHDU, PPC_MULHW, PPC_MULHWU,
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PPC_MULLD, PPC_MULLI, PPC_MULLW, PPC_NAND, PPC_NEG, PPC_NOR, PPC_NOP,
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PPC_OR, PPC_ORC, PPC_ORI, PPC_ORIS, PPC_POPCNTB, PPC_POPCNTD,
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PPC_POPCNTW, PPC_PRTYD, PPC_PRTYW, PPC_RLDCL, PPC_RLDCR,
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PPC_RLDIC, PPC_RLDICL, PPC_RLDICR, PPC_RLDIMI, PPC_RLWIMI,
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PPC_RLWINM, PPC_RLWNM, PPC_SETB, PPC_SLD, PPC_SLW, PPC_SRAD,
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PPC_SRADI, PPC_SRAW, PPC_SRAWI, PPC_SRD, PPC_SRW, PPC_STB,
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PPC_STBCX, PPC_STBU, PPC_STBUX, PPC_STBX, PPC_STD, PPC_STDBRX,
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PPC_STDCX, PPC_STDU, PPC_STDUX, PPC_STDX, PPC_STH, PPC_STHBRX,
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PPC_STHCX, PPC_STHU, PPC_STHUX, PPC_STHX, PPC_STW, PPC_STWBRX,
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PPC_STWCX, PPC_STWU, PPC_STWUX, PPC_STWX, PPC_SUBF, PPC_SUBFC,
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PPC_SUBFE, PPC_SUBFIC, PPC_SUBFME, PPC_SUBFZE, PPC_SYNC, PPC_TD,
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PPC_TDI, PPC_TW, PPC_TWI, PPC_XOR, PPC_XORI, PPC_XORIS,
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PPC_SIM_CONFIG);
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type insn_type_t is (OP_ILLEGAL, OP_NOP, OP_ADD, OP_ADDE, OP_ADDEX, OP_ADDME,
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OP_ADDPCIS, OP_AND, OP_ANDC, OP_ATTN, OP_B, OP_BC,
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OP_BCCTR, OP_BCLR, OP_BCTAR, OP_BPERM, OP_CMP,
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OP_CMPB, OP_CMPEQB, OP_CMPL, OP_CMPRB,
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OP_CNTLZD, OP_CNTLZW, OP_CNTTZD, OP_CNTTZW, OP_CRAND,
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OP_CRANDC, OP_CREQV, OP_CRNAND, OP_CRNOR, OP_CROR, OP_CRORC,
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OP_CRXOR, OP_DARN, OP_DCBF, OP_DCBST, OP_DCBT, OP_DCBTST,
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OP_DCBZ, OP_DIV, OP_EQV, OP_EXTSB, OP_EXTSH,
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OP_EXTSW, OP_EXTSWSLI, OP_ICBI, OP_ICBT, OP_ISEL, OP_ISYNC,
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OP_LOAD, OP_STORE, OP_MADDHD, OP_MADDHDU, OP_MADDLD, OP_MCRF,
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OP_MCRXR, OP_MCRXRX, OP_MFCR, OP_MFOCRF, OP_MFSPR, OP_MOD,
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OP_MTCRF, OP_MTOCRF, OP_MTSPR, OP_MUL_L64,
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OP_MUL_H64, OP_MUL_H32, OP_NAND, OP_NEG, OP_NOR, OP_OR,
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OP_ORC, OP_POPCNTB, OP_POPCNTD, OP_POPCNTW, OP_PRTYD,
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OP_PRTYW, OP_RLDCL, OP_RLDCR, OP_RLDIC, OP_RLDICL, OP_RLDICR,
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OP_RLDIMI, OP_RLWIMI, OP_RLWINM, OP_RLWNM, OP_SETB, OP_SLD,
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OP_SLW, OP_SRAD, OP_SRADI, OP_SRAW, OP_SRAWI, OP_SRD, OP_SRW,
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OP_SUBF, OP_SUBFE, OP_SUBFME, OP_SYNC, OP_TD, OP_TDI, OP_TW,
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OP_TWI, OP_XOR, OP_SIM_CONFIG);
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type input_reg_a_t is (NONE, RA, RA_OR_ZERO, RS);
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type input_reg_b_t is (NONE, RB, RS, CONST_UI, CONST_SI, CONST_SI_HI, CONST_UI_HI, CONST_LI, CONST_BD, CONST_DS);
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type input_reg_c_t is (NONE, RS);
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type output_reg_a_t is (NONE, RT, RA);
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type constant_a_t is (NONE, SH, SH32, FXM, BO, BF, TOO, BC);
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type constant_b_t is (NONE, MB, ME, MB32, BI, L, BFA);
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type constant_c_t is (NONE, ME32, BH);
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type rc_t is (NONE, ONE, RC);
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constant SH_OFFSET : integer := 0;
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constant MB_OFFSET : integer := 1;
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constant ME_OFFSET : integer := 1;
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constant SH32_OFFSET : integer := 0;
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constant MB32_OFFSET : integer := 1;
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constant ME32_OFFSET : integer := 2;
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constant FXM_OFFSET : integer := 0;
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constant BO_OFFSET : integer := 0;
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constant BI_OFFSET : integer := 1;
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constant BH_OFFSET : integer := 2;
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constant BF_OFFSET : integer := 0;
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constant L_OFFSET : integer := 1;
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constant TOO_OFFSET : integer := 0;
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type unit_t is (NONE, ALU, LDST, MUL, DIV);
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type length_t is (NONE, is1B, is2B, is4B, is8B);
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type decode_rom_t is record
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unit : unit_t;
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insn_type : insn_type_t;
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input_reg_a : input_reg_a_t;
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input_reg_b : input_reg_b_t;
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input_reg_c : input_reg_c_t;
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output_reg_a : output_reg_a_t;
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const_a : constant_a_t;
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const_b : constant_b_t;
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const_c : constant_c_t;
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input_cr : std_ulogic;
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output_cr : std_ulogic;
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input_carry : std_ulogic;
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output_carry : std_ulogic;
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-- load/store signals
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length : length_t;
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byte_reverse : std_ulogic;
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sign_extend : std_ulogic;
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update : std_ulogic;
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reserve : std_ulogic;
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-- multiplier signals
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mul_32bit : std_ulogic;
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mul_signed : std_ulogic;
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rc : rc_t;
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lr : std_ulogic;
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sgl_pipe : std_ulogic;
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end record;
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constant decode_rom_init : decode_rom_t := (unit => NONE,
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insn_type => OP_ILLEGAL, input_reg_a => NONE,
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input_reg_b => NONE, input_reg_c => NONE,
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output_reg_a => NONE, const_a => NONE, const_b => NONE,
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const_c => NONE, input_cr => '0', output_cr => '0',
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input_carry => '0', output_carry => '0',
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length => NONE, byte_reverse => '0', sign_extend => '0',
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update => '0', reserve => '0', mul_32bit => '0',
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mul_signed => '0', rc => NONE, lr => '0', sgl_pipe => '0');
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end decode_types;
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package body decode_types is
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end decode_types;
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