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2f45e545ed
At present the busy/stall signal going to decode1 depends on whether control thinks it can issue the current instruction, and that depends on completion and bypass signals coming from execute1 and writeback. To improve the timing of stall_out, this rearranges decode2 so that stall_out is asserted when we have a valid instruction that couldn't be issued in the previous cycle. This means that decode1 could give us a new instruction when we haven't issued the previous instruction. This in turn means that we can only use d_in in the first cycle of processing an instruction. After the first cycle, we get register addresses etc. from dc2 rather than d_in. Then, to avoid the need to read register operands from register_file in each cycle until the instruction issues, we bring the bypass path for data being written to the register file into decode2 explicitly rather than having it in register_file. A new process called decode2_addrs does the process of calling decode_input_reg_* and decode_output_reg and sets up the register file addresses. This was split out (and decode_input_reg_* reworked) to try to reduce the number of passes through the decode2_1 process that need to be done in simulation. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
228 lines
7.7 KiB
VHDL
228 lines
7.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.crhelpers.all;
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entity writeback is
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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e_in : in Execute1ToWritebackType;
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l_in : in Loadstore1ToWritebackType;
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fp_in : in FPUToWritebackType;
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w_out : out WritebackToRegisterFileType;
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c_out : out WritebackToCrFileType;
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f_out : out WritebackToFetch1Type;
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wb_bypass : out bypass_data_t;
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-- PMU event bus
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events : out WritebackEventType;
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flush_out : out std_ulogic;
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interrupt_out: out std_ulogic;
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complete_out : out instr_tag_t
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);
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end entity writeback;
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architecture behaviour of writeback is
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type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
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type reg_type is record
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state : irq_state_t;
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srr1 : std_ulogic_vector(63 downto 0);
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end record;
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signal r, rin : reg_type;
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begin
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writeback_0: process(clk)
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variable x : std_ulogic_vector(0 downto 0);
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variable y : std_ulogic_vector(0 downto 0);
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variable w : std_ulogic_vector(0 downto 0);
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begin
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if rising_edge(clk) then
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if rst = '1' then
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r.state <= WRITE_SRR0;
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r.srr1 <= (others => '0');
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else
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r <= rin;
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end if;
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-- Do consistency checks only on the clock edge
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x(0) := e_in.valid;
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y(0) := l_in.valid;
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w(0) := fp_in.valid;
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assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) +
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to_integer(unsigned(w))) <= 1 severity failure;
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x(0) := e_in.write_enable;
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y(0) := l_in.write_enable;
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w(0) := fp_in.write_enable;
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assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) +
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to_integer(unsigned(w))) <= 1 severity failure;
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w(0) := e_in.write_cr_enable;
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x(0) := l_in.rc;
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y(0) := fp_in.write_cr_enable;
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assert (to_integer(unsigned(w)) + to_integer(unsigned(x)) +
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to_integer(unsigned(y))) <= 1 severity failure;
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assert not (e_in.valid = '1' and e_in.instr_tag.valid = '0') severity failure;
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assert not (l_in.valid = '1' and l_in.instr_tag.valid = '0') severity failure;
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assert not (fp_in.valid = '1' and fp_in.instr_tag.valid = '0') severity failure;
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end if;
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end process;
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writeback_1: process(all)
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variable v : reg_type;
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variable f : WritebackToFetch1Type;
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variable scf : std_ulogic_vector(3 downto 0);
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variable vec : integer range 0 to 16#fff#;
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variable srr1 : std_ulogic_vector(15 downto 0);
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variable intr : std_ulogic;
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begin
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w_out <= WritebackToRegisterFileInit;
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c_out <= WritebackToCrFileInit;
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f := WritebackToFetch1Init;
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interrupt_out <= '0';
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vec := 0;
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v := r;
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complete_out <= instr_tag_init;
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if e_in.valid = '1' then
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complete_out <= e_in.instr_tag;
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elsif l_in.valid = '1' then
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complete_out <= l_in.instr_tag;
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elsif fp_in.valid = '1' then
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complete_out <= fp_in.instr_tag;
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end if;
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events.instr_complete <= complete_out.valid;
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events.fp_complete <= fp_in.valid;
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intr := e_in.interrupt or l_in.interrupt or fp_in.interrupt;
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if r.state = WRITE_SRR1 then
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w_out.write_reg <= fast_spr_num(SPR_SRR1);
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w_out.write_data <= r.srr1;
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w_out.write_enable <= '1';
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interrupt_out <= '1';
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v.state := WRITE_SRR0;
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elsif intr = '1' then
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w_out.write_reg <= fast_spr_num(SPR_SRR0);
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w_out.write_enable <= '1';
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v.state := WRITE_SRR1;
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srr1 := (others => '0');
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if e_in.interrupt = '1' then
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vec := e_in.intr_vec;
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w_out.write_data <= e_in.last_nia;
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srr1 := e_in.srr1;
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elsif l_in.interrupt = '1' then
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vec := l_in.intr_vec;
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w_out.write_data <= l_in.srr0;
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srr1 := l_in.srr1;
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elsif fp_in.interrupt = '1' then
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vec := fp_in.intr_vec;
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w_out.write_data <= fp_in.srr0;
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srr1 := fp_in.srr1;
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end if;
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v.srr1(63 downto 31) := e_in.msr(63 downto 31);
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v.srr1(30 downto 27) := srr1(14 downto 11);
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v.srr1(26 downto 22) := e_in.msr(26 downto 22);
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v.srr1(21 downto 16) := srr1(5 downto 0);
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v.srr1(15 downto 0) := e_in.msr(15 downto 0);
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else
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if e_in.write_enable = '1' then
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w_out.write_reg <= e_in.write_reg;
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w_out.write_data <= e_in.write_data;
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w_out.write_enable <= '1';
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end if;
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if e_in.write_cr_enable = '1' then
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c_out.write_cr_enable <= '1';
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c_out.write_cr_mask <= e_in.write_cr_mask;
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c_out.write_cr_data <= e_in.write_cr_data;
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end if;
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if e_in.write_xerc_enable = '1' then
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c_out.write_xerc_enable <= '1';
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c_out.write_xerc_data <= e_in.xerc;
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end if;
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if fp_in.write_enable = '1' then
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w_out.write_reg <= fp_in.write_reg;
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w_out.write_data <= fp_in.write_data;
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w_out.write_enable <= '1';
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end if;
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if fp_in.write_cr_enable = '1' then
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c_out.write_cr_enable <= '1';
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c_out.write_cr_mask <= fp_in.write_cr_mask;
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c_out.write_cr_data <= fp_in.write_cr_data;
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end if;
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if l_in.write_enable = '1' then
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w_out.write_reg <= l_in.write_reg;
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w_out.write_data <= l_in.write_data;
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w_out.write_enable <= '1';
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end if;
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if l_in.rc = '1' then
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-- st*cx. instructions
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scf(3) := '0';
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scf(2) := '0';
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scf(1) := l_in.store_done;
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scf(0) := l_in.xerc.so;
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c_out.write_cr_enable <= '1';
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c_out.write_cr_mask <= num_to_fxm(0);
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c_out.write_cr_data(31 downto 28) <= scf;
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end if;
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end if;
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-- Outputs to fetch1
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f.redirect := e_in.redirect;
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f.br_nia := e_in.last_nia;
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f.br_last := e_in.br_last;
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f.br_taken := e_in.br_taken;
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if intr = '1' then
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f.redirect := '1';
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f.br_last := '0';
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f.redirect_nia := std_ulogic_vector(to_unsigned(vec, 64));
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f.virt_mode := '0';
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f.priv_mode := '1';
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-- XXX need an interrupt LE bit here, e.g. from LPCR
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f.big_endian := '0';
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f.mode_32bit := '0';
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else
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if e_in.abs_br = '1' then
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f.redirect_nia := e_in.br_offset;
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else
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f.redirect_nia := std_ulogic_vector(unsigned(e_in.last_nia) + unsigned(e_in.br_offset));
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end if;
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-- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
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f.virt_mode := e_in.redir_mode(3);
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f.priv_mode := e_in.redir_mode(2);
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f.big_endian := e_in.redir_mode(1);
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f.mode_32bit := e_in.redir_mode(0);
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end if;
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f_out <= f;
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flush_out <= f_out.redirect;
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-- Register write data bypass to decode2
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wb_bypass.tag.tag <= complete_out.tag;
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wb_bypass.tag.valid <= complete_out.valid and w_out.write_enable;
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wb_bypass.data <= w_out.write_data;
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rin <= v;
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end process;
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end;
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