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5d85ede97d
This involves plumbing the (existing) 'reserve' and 'rc' bits in the decode tables down to dcache, and 'rc' and 'store_done' bits from dcache to writeback. It turns out that we had 'RC' set in the 'rc' column for several ordinary stores and for the attn instruction. This corrects them to 'NONE', and sets the 'rc' column to 'ONE' for the conditional stores. In writeback we now have logic to set CR0 when the input from dcache has rc = 1. In dcache we have the reservation itself, which has a valid bit and the address down to cache line granularity. We don't currently store the reservation length. For a store conditional which fails, we set a 'cancel_store' signal which inhibits the write to the cache and prevents the state machine from starting a bus cycle or going to the STORE_WAIT_ACK state. Instead we set r1.stcx_fail which causes the instruction to complete in the next cycle with rc=1 and store_done=0. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
204 lines
6.9 KiB
VHDL
204 lines
6.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.crhelpers.all;
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entity writeback is
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port (
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clk : in std_ulogic;
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e_in : in Execute1ToWritebackType;
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l_in : in DcacheToWritebackType;
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w_out : out WritebackToRegisterFileType;
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c_out : out WritebackToCrFileType;
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complete_out : out std_ulogic
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);
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end entity writeback;
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architecture behaviour of writeback is
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subtype byte_index_t is unsigned(2 downto 0);
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type permutation_t is array(0 to 7) of byte_index_t;
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subtype byte_trim_t is std_ulogic_vector(1 downto 0);
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type trim_ctl_t is array(0 to 7) of byte_trim_t;
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type byte_sel_t is array(0 to 7) of std_ulogic;
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signal data_len : unsigned(3 downto 0);
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signal data_in : std_ulogic_vector(63 downto 0);
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signal data_permuted : std_ulogic_vector(63 downto 0);
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signal data_trimmed : std_ulogic_vector(63 downto 0);
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signal data_latched : std_ulogic_vector(63 downto 0);
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signal perm : permutation_t;
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signal use_second : byte_sel_t;
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signal byte_offset : unsigned(2 downto 0);
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signal brev_lenm1 : unsigned(2 downto 0);
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signal trim_ctl : trim_ctl_t;
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signal rc : std_ulogic;
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signal partial_write : std_ulogic;
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signal sign_extend : std_ulogic;
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signal negative : std_ulogic;
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signal second_word : std_ulogic;
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begin
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writeback_0: process(clk)
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begin
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if rising_edge(clk) then
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if partial_write = '1' then
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data_latched <= data_permuted;
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end if;
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end if;
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end process;
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writeback_1: process(all)
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variable x : std_ulogic_vector(0 downto 0);
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variable y : std_ulogic_vector(0 downto 0);
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variable z : std_ulogic_vector(0 downto 0);
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variable w : std_ulogic_vector(0 downto 0);
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variable j : integer;
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variable k : unsigned(3 downto 0);
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variable cf: std_ulogic_vector(3 downto 0);
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variable xe: xer_common_t;
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variable zero : std_ulogic;
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variable sign : std_ulogic;
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variable scf : std_ulogic_vector(3 downto 0);
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begin
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x(0) := e_in.valid;
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y(0) := l_in.valid;
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assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure;
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x(0) := e_in.write_enable;
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y(0) := l_in.write_enable;
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assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure;
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w(0) := e_in.write_cr_enable;
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x(0) := (e_in.write_enable and e_in.rc);
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assert (to_integer(unsigned(w)) + to_integer(unsigned(x))) <= 1 severity failure;
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w_out <= WritebackToRegisterFileInit;
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c_out <= WritebackToCrFileInit;
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complete_out <= '0';
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if e_in.valid = '1' or l_in.valid = '1' then
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complete_out <= '1';
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end if;
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rc <= '0';
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brev_lenm1 <= "000";
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partial_write <= '0';
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second_word <= '0';
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xe := e_in.xerc;
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data_in <= (others => '0');
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if e_in.write_enable = '1' then
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w_out.write_reg <= e_in.write_reg;
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w_out.write_enable <= '1';
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rc <= e_in.rc;
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end if;
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if e_in.write_cr_enable = '1' then
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c_out.write_cr_enable <= '1';
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c_out.write_cr_mask <= e_in.write_cr_mask;
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c_out.write_cr_data <= e_in.write_cr_data;
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end if;
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if e_in.write_xerc_enable = '1' then
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c_out.write_xerc_enable <= '1';
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c_out.write_xerc_data <= e_in.xerc;
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end if;
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sign_extend <= l_in.sign_extend;
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data_len <= unsigned(l_in.write_len);
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byte_offset <= unsigned(l_in.write_shift);
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if l_in.write_enable = '1' then
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w_out.write_reg <= gpr_to_gspr(l_in.write_reg);
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if l_in.byte_reverse = '1' then
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brev_lenm1 <= unsigned(l_in.write_len(2 downto 0)) - 1;
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end if;
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second_word <= l_in.second_word;
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if l_in.valid = '0' and (data_len + byte_offset > 8) then
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partial_write <= '1';
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end if;
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xe := l_in.xerc;
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w_out.write_enable <= not partial_write or second_word;
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end if;
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if l_in.rc = '1' then
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-- st*cx. instructions
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scf(3) := '0';
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scf(2) := '0';
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scf(1) := l_in.store_done;
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scf(0) := xe.so;
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c_out.write_cr_enable <= '1';
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c_out.write_cr_mask <= num_to_fxm(0);
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c_out.write_cr_data(31 downto 28) <= scf;
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end if;
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-- shift and byte-reverse data bytes
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for i in 0 to 7 loop
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k := ('0' & (to_unsigned(i, 3) xor brev_lenm1)) + ('0' & byte_offset);
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perm(i) <= k(2 downto 0);
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use_second(i) <= k(3);
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end loop;
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for i in 0 to 7 loop
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j := to_integer(perm(i)) * 8;
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data_permuted(i * 8 + 7 downto i * 8) <= l_in.write_data(j + 7 downto j);
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end loop;
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-- If the data can arrive split over two cycles, this will be correct
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-- provided we don't have both sign extension and byte reversal.
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negative <= (data_len(3) and data_permuted(63)) or
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(data_len(2) and data_permuted(31)) or
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(data_len(1) and data_permuted(15)) or
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(data_len(0) and data_permuted(7));
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-- trim and sign-extend
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for i in 0 to 7 loop
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if i < to_integer(data_len) then
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if second_word = '1' then
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trim_ctl(i) <= '1' & not use_second(i);
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else
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trim_ctl(i) <= not use_second(i) & '0';
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end if;
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else
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trim_ctl(i) <= '0' & (negative and sign_extend);
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end if;
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end loop;
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for i in 0 to 7 loop
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case trim_ctl(i) is
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when "11" =>
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data_trimmed(i * 8 + 7 downto i * 8) <= data_latched(i * 8 + 7 downto i * 8);
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when "10" =>
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data_trimmed(i * 8 + 7 downto i * 8) <= data_permuted(i * 8 + 7 downto i * 8);
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when "01" =>
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data_trimmed(i * 8 + 7 downto i * 8) <= x"FF";
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when others =>
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data_trimmed(i * 8 + 7 downto i * 8) <= x"00";
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end case;
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end loop;
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-- deliver to regfile
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if l_in.write_enable = '1' then
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w_out.write_data <= data_trimmed;
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else
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w_out.write_data <= e_in.write_data;
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end if;
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-- Perform CR0 update for RC forms
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-- Note that loads never have a form with an RC bit, therefore this can test e_in.write_data
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if rc = '1' then
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sign := e_in.write_data(63);
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zero := not (or e_in.write_data);
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c_out.write_cr_enable <= '1';
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c_out.write_cr_mask <= num_to_fxm(0);
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cf(3) := sign;
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cf(2) := not sign and not zero;
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cf(1) := zero;
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cf(0) := xe.so;
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c_out.write_cr_data(31 downto 28) <= cf;
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end if;
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end process;
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end;
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