mirror of
https://github.com/antonblanchard/microwatt.git
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a3857aac94
This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
47 lines
1.0 KiB
C
47 lines
1.0 KiB
C
#ifndef __SYSTEM_H
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#define __SYSTEM_H
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#include "microwatt_soc.h"
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#include "io.h"
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#define CSR_ACCESSORS_DEFINED
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#define CSR_BASE DRAM_CTRL_BASE
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#define CONFIG_CPU_NOP "nop"
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#ifdef __SIM__
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#define MEMTEST_BUS_SIZE 512//16
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#define MEMTEST_DATA_SIZE 1024//16
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#define MEMTEST_ADDR_SIZE 128//16
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#define CONFIG_SIM_DISABLE_DELAYS
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#endif
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extern void flush_cpu_dcache(void);
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extern void flush_cpu_icache(void);
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static inline void flush_l2_cache(void) { }
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/* Fake timer stuff. LiteX should abstract this */
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static inline void timer0_en_write(int e) { }
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static inline void timer0_reload_write(int r) { }
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static inline void timer0_load_write(int l) { }
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static inline void timer0_update_value_write(int v) { }
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static inline uint64_t timer0_value_read(void)
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{
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uint64_t val;
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__asm__ volatile ("mfdec %0" : "=r" (val));
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return val;
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}
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static inline void csr_write_simple(unsigned long v, unsigned long a)
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{
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return writel(v, a);
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}
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static inline unsigned long csr_read_simple(unsigned long a)
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{
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return readl(a);
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}
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#endif /* __SYSTEM_H */
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