mirror of
https://github.com/antonblanchard/microwatt.git
synced 2026-02-05 15:55:00 +00:00
599fad117b
Support for this has bitrotted and would require refactoring of L2 to be brought back. It's also not really needed anymore now that we ship pre-generated litedram and that LiteX supports what we do. So take it out, which simplifies some of the scripts as well. This also fixes up CSR alignment the sim model. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
44 lines
1.8 KiB
YAML
44 lines
1.8 KiB
YAML
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
|
|
# License: BSD
|
|
|
|
{
|
|
# General ------------------------------------------------------------------
|
|
"cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32)
|
|
"cpu_variant":"standard",
|
|
"speedgrade": -1, # FPGA speedgrade
|
|
"memtype": "DDR3", # DRAM type
|
|
"sim" : "True",
|
|
|
|
# PHY ----------------------------------------------------------------------
|
|
"cmd_delay": 0, # Command additional delay (in taps)
|
|
"cmd_latency": 0, # Command additional latency
|
|
"sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM
|
|
"sdram_module_nb": 2, # Number of byte groups
|
|
"sdram_rank_nb": 1, # Number of ranks
|
|
"sdram_phy": "A7DDRPHY", # Type of FPGA PHY
|
|
|
|
# Electrical ---------------------------------------------------------------
|
|
"rtt_nom": "60ohm", # Nominal termination
|
|
"rtt_wr": "60ohm", # Write termination
|
|
"ron": "34ohm", # Output driver impedance
|
|
|
|
# Frequency ----------------------------------------------------------------
|
|
"input_clk_freq": 100e6, # Input clock frequency
|
|
"sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
|
|
"iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
|
|
|
|
# Core ---------------------------------------------------------------------
|
|
"cmd_buffer_depth": 16, # Depth of the command buffer
|
|
|
|
# User Ports ---------------------------------------------------------------
|
|
"user_ports": {
|
|
"native_0": {
|
|
"type": "native",
|
|
},
|
|
},
|
|
|
|
# CSR Port -----------------------------------------------------------------
|
|
"csr_alignment" : 32,
|
|
"csr_data_width" : 32,
|
|
}
|