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antonblanchard.microwatt/tests
Paul Mackerras f631dcd700 FPU: Set FPRF correctly on multiply result that underflows
rcls_op being set to RCLS_TZERO was not detecting a zero result after
rounding for a multiply result that underflows, because S still had
low bits of the product.  To fix this, remove the 's_nz = 0' from the
RCLS_TZERO test.  We can't then use this test in the FMADD_6 state,
but we really shouldn't be testing for zero there, before rounding,
so remove that.  Also simplify FMADD_6 state by not setting rs_norm
and going always to FINISH state rather than going to NORMALIZE state.

Add a test for this case (actually a fmadd with B=0).

While here, remove a pointless assignment to f_to_multiply.valid in
MULT_1 state, since r.first is never set here.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2025-12-15 08:45:23 +11:00
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