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https://github.com/antonblanchard/microwatt.git
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A first pass at ghdl synthesis using yosys and nextpnr. It runs hello world or micropython if the FPGA has enough block RAM (eg ECP5 85F). The hello world testcase also loops UART rx to tx in software (ie not a hardware loopback). It uses Docker images, so no software needs to be installed. If you prefer podman you can use that too. Edit Makefile.synth to configure your FPGA, JTAG device etc. To build: make -f Makefile.synth and to program: make -f Makefile.synth prog A few issues: We need to add PLL support. Right now Microwatt runs at whatever the external clock frequency is and the baud rate gets scaled by how far off 50MHz it is. This means on the ecp5-evn with a 12 MHz clock rate the baud rate is a quite strange 27650 (115200 * 50 / 12). On my OrangeCrab with a 50MHz clock the UART is 115200. It uses a large amount of resources, way more than it should. There are still some ghdl/yosys issues to be sorted out. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
78 lines
2.8 KiB
Makefile
78 lines
2.8 KiB
Makefile
# Use local tools
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#GHDLSYNTH = ghdl.so
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#YOSYS = yosys
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#NEXTPNR = nextpnr-ecp5
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#ECPPACK = ecppack
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#OPENOCD = openocd
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# Use Docker images
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DOCKER=docker
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#DOCKER=podman
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#
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PWD = $(shell pwd)
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DOCKERARGS = run --rm -v $(PWD):/src -w /src
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#
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GHDLSYNTH = ghdl
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YOSYS = $(DOCKER) $(DOCKERARGS) ghdl/synth:beta yosys
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NEXTPNR = $(DOCKER) $(DOCKERARGS) ghdl/synth:nextpnr-ecp5 nextpnr-ecp5
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ECPPACK = $(DOCKER) $(DOCKERARGS) ghdl/synth:trellis ecppack
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OPENOCD = $(DOCKER) $(DOCKERARGS) --device /dev/bus/usb ghdl/synth:prog openocd
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# Hello world
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GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=8192 -gRAM_INIT_FILE=hello_world/hello_world.hex
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# Micropython
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#GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=393216 -gRAM_INIT_FILE=micropython/firmware.hex
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# OrangeCrab with ECP85
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#GHDL_TARGET_GENERICS=-gRESET_LOW=true -gCLK_INPUT=50000000 -gCLK_FREQUENCY=50000000
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#LPF=constraints/orange-crab.lpf
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#PACKAGE=CSFBGA285
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#NEXTPNR_FLAGS=--um5g-85k --freq 50
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#OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
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#OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
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# ECP5-EVN
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GHDL_TARGET_GENERICS=-gRESET_LOW=true -gCLK_INPUT=12000000 -gCLK_FREQUENCY=12000000
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LPF=constraints/ecp5-evn.lpf
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PACKAGE=CABGA381
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NEXTPNR_FLAGS=--um5g-85k --freq 12
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OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
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OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
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VHDL_FILES = wishbone_types.vhdl utils.vhdl fpga/main_bram.vhdl
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VHDL_FILES += wishbone_bram_wrapper.vhdl decode_types.vhdl common.vhdl
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VHDL_FILES += fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd wishbone_arbiter.vhdl
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VHDL_FILES += dmi_dtm_dummy.vhdl wishbone_debug_master.vhdl helpers.vhdl
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VHDL_FILES += loadstore1.vhdl crhelpers.vhdl writeback.vhdl ppc_fx_insns.vhdl
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VHDL_FILES += countzero.vhdl insn_helpers.vhdl rotator.vhdl logical.vhdl
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VHDL_FILES += execute1.vhdl fetch1.vhdl gpr_hazard.vhdl cr_hazard.vhdl
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VHDL_FILES += control.vhdl decode2.vhdl cr_file.vhdl cache_ram.vhdl plru.vhdl
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VHDL_FILES += dcache.vhdl core_debug.vhdl multiply.vhdl icache.vhdl fetch2.vhdl
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VHDL_FILES += register_file.vhdl decode1.vhdl divider.vhdl core.vhdl soc.vhdl
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VHDL_FILES += fpga/soc_reset.vhdl fpga/clk_gen_bypass.vhd fpga/toplevel.vhdl
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all: microwatt.bit
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microwatt.json: $(VHDL_FILES)
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$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(VHDL_FILES) -e toplevel; synth_ecp5 -json $@"
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microwatt_out.config: microwatt.json $(LPF)
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$(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@ $(NEXTPNR_FLAGS) --package $(PACKAGE)
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microwatt.bit: microwatt_out.config
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$(ECPPACK) --svf microwatt.svf $< $@
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microwatt.svf: microwatt.bit
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prog: microwatt.svf
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$(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"
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clean:
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@rm -f work-obj08.cf *.bit *.json *.svf *.config
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.PHONY: clean prog
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.PRECIOUS: microwatt.json microwatt_out.config microwatt.bit
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