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https://github.com/antonblanchard/microwatt.git
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49a4d9f67a
This logs 256 bits of data per cycle to a ring buffer in BRAM. The data collected can be read out through 2 new SPRs or through the debug interface. The new SPRs are LOG_ADDR (724) and LOG_DATA (725). LOG_ADDR contains the buffer write pointer in the upper 32 bits (in units of entries, i.e. 32 bytes) and the read pointer in the lower 32 bits (in units of doublewords, i.e. 8 bytes). Reading LOG_DATA gives the doubleword from the buffer at the read pointer and increments the read pointer. Setting bit 31 of LOG_ADDR inhibits the trace log system from writing to the log buffer, so the contents are stable and can be read. There are two new debug addresses which function similarly to the LOG_ADDR and LOG_DATA SPRs. The log is frozen while either or both of the LOG_ADDR SPR bit 31 or the debug LOG_ADDR register bit 31 are set. The buffer defaults to 2048 entries, i.e. 64kB. The size is set by the LOG_LENGTH generic on the core_debug module. Software can determine the length of the buffer because the length is ORed into the buffer write pointer in the upper 32 bits of LOG_ADDR. Hence the length of the buffer can be calculated as 1 << (31 - clz(LOG_ADDR)). There is a program to format the log entries in a somewhat readable fashion in scripts/fmt_log/fmt_log.c. The log_entry struct in that file describes the layout of the bits in the log entries. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
291 lines
9.9 KiB
VHDL
291 lines
9.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.utils.all;
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use work.common.all;
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entity core_debug is
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generic (
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-- Length of log buffer
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LOG_LENGTH : positive := 2048
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);
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port (
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clk : in std_logic;
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rst : in std_logic;
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dmi_addr : in std_ulogic_vector(3 downto 0);
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dmi_din : in std_ulogic_vector(63 downto 0);
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dmi_dout : out std_ulogic_vector(63 downto 0);
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dmi_req : in std_ulogic;
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dmi_wr : in std_ulogic;
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dmi_ack : out std_ulogic;
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-- Debug actions
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core_stop : out std_ulogic;
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core_rst : out std_ulogic;
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icache_rst : out std_ulogic;
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-- Core status inputs
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terminate : in std_ulogic;
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core_stopped : in std_ulogic;
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nia : in std_ulogic_vector(63 downto 0);
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msr : in std_ulogic_vector(63 downto 0);
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-- GSPR register read port
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dbg_gpr_req : out std_ulogic;
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dbg_gpr_ack : in std_ulogic;
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dbg_gpr_addr : out gspr_index_t;
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dbg_gpr_data : in std_ulogic_vector(63 downto 0);
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-- Core logging data
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log_data : in std_ulogic_vector(255 downto 0);
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log_read_addr : in std_ulogic_vector(31 downto 0);
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log_read_data : out std_ulogic_vector(63 downto 0);
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log_write_addr : out std_ulogic_vector(31 downto 0);
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-- Misc
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terminated_out : out std_ulogic
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);
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end core_debug;
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architecture behave of core_debug is
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-- DMI needs fixing... make a one clock pulse
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signal dmi_req_1: std_ulogic;
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-- CTRL register (direct actions, write 1 to act, read back 0)
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-- bit 0 : Core stop
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-- bit 1 : Core reset (doesn't clear stop)
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-- bit 2 : Icache reset
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-- bit 3 : Single step
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-- bit 4 : Core start
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constant DBG_CORE_CTRL : std_ulogic_vector(3 downto 0) := "0000";
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constant DBG_CORE_CTRL_STOP : integer := 0;
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constant DBG_CORE_CTRL_RESET : integer := 1;
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constant DBG_CORE_CTRL_ICRESET : integer := 2;
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constant DBG_CORE_CTRL_STEP : integer := 3;
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constant DBG_CORE_CTRL_START : integer := 4;
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-- STAT register (read only)
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-- bit 0 : Core stopping (wait til bit 1 set)
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-- bit 1 : Core stopped
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-- bit 2 : Core terminated (clears with start or reset)
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constant DBG_CORE_STAT : std_ulogic_vector(3 downto 0) := "0001";
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constant DBG_CORE_STAT_STOPPING : integer := 0;
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constant DBG_CORE_STAT_STOPPED : integer := 1;
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constant DBG_CORE_STAT_TERM : integer := 2;
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-- NIA register (read only for now)
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constant DBG_CORE_NIA : std_ulogic_vector(3 downto 0) := "0010";
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-- MSR (read only)
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constant DBG_CORE_MSR : std_ulogic_vector(3 downto 0) := "0011";
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-- GSPR register index
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constant DBG_CORE_GSPR_INDEX : std_ulogic_vector(3 downto 0) := "0100";
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-- GSPR register data
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constant DBG_CORE_GSPR_DATA : std_ulogic_vector(3 downto 0) := "0101";
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-- Log buffer address and data registers
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constant DBG_CORE_LOG_ADDR : std_ulogic_vector(3 downto 0) := "0110";
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constant DBG_CORE_LOG_DATA : std_ulogic_vector(3 downto 0) := "0111";
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-- Some internal wires
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signal stat_reg : std_ulogic_vector(63 downto 0);
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-- Some internal latches
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signal stopping : std_ulogic;
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signal do_step : std_ulogic;
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signal do_reset : std_ulogic;
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signal do_icreset : std_ulogic;
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signal terminated : std_ulogic;
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signal do_gspr_rd : std_ulogic;
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signal gspr_index : gspr_index_t;
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-- Logging RAM
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constant LOG_INDEX_BITS : natural := log2(LOG_LENGTH);
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subtype log_ptr_t is unsigned(LOG_INDEX_BITS - 1 downto 0);
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type log_array_t is array(0 to LOG_LENGTH - 1) of std_ulogic_vector(255 downto 0);
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signal log_array : log_array_t;
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signal log_rd_ptr : log_ptr_t;
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signal log_wr_ptr : log_ptr_t;
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signal log_toggle : std_ulogic;
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signal log_wr_enable : std_ulogic;
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signal log_rd_ptr_latched : log_ptr_t;
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signal log_rd : std_ulogic_vector(255 downto 0);
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signal log_dmi_addr : std_ulogic_vector(31 downto 0);
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signal log_dmi_data : std_ulogic_vector(63 downto 0);
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signal do_dmi_log_rd : std_ulogic;
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signal log_dmi_reading : std_ulogic;
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signal log_dmi_read_done : std_ulogic;
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signal dmi_read_log_data : std_ulogic;
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signal dmi_read_log_data_1 : std_ulogic;
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function select_dword(data : std_ulogic_vector(255 downto 0);
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addr : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
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variable firstbit : integer;
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begin
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firstbit := to_integer(unsigned(addr(1 downto 0))) * 64;
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return data(firstbit + 63 downto firstbit);
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end;
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attribute ram_style : string;
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attribute ram_style of log_array : signal is "block";
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attribute ram_decomp : string;
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attribute ram_decomp of log_array : signal is "power";
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begin
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-- Single cycle register accesses on DMI except for GSPR data
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dmi_ack <= dmi_req when dmi_addr /= DBG_CORE_GSPR_DATA
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else dbg_gpr_ack;
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dbg_gpr_req <= dmi_req when dmi_addr = DBG_CORE_GSPR_DATA
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else '0';
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-- Status register read composition
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stat_reg <= (2 => terminated,
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1 => core_stopped,
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0 => stopping,
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others => '0');
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-- DMI read data mux
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with dmi_addr select dmi_dout <=
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stat_reg when DBG_CORE_STAT,
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nia when DBG_CORE_NIA,
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msr when DBG_CORE_MSR,
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dbg_gpr_data when DBG_CORE_GSPR_DATA,
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log_write_addr & log_dmi_addr when DBG_CORE_LOG_ADDR,
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log_dmi_data when DBG_CORE_LOG_DATA,
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(others => '0') when others;
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-- DMI writes
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reg_write: process(clk)
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begin
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if rising_edge(clk) then
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-- Reset the 1-cycle "do" signals
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do_step <= '0';
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do_reset <= '0';
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do_icreset <= '0';
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do_dmi_log_rd <= '0';
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if (rst) then
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stopping <= '0';
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terminated <= '0';
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else
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-- Edge detect on dmi_req for 1-shot pulses
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dmi_req_1 <= dmi_req;
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if dmi_req = '1' and dmi_req_1 = '0' then
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if dmi_wr = '1' then
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report("DMI write to " & to_hstring(dmi_addr));
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-- Control register actions
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if dmi_addr = DBG_CORE_CTRL then
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if dmi_din(DBG_CORE_CTRL_RESET) = '1' then
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do_reset <= '1';
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terminated <= '0';
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end if;
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if dmi_din(DBG_CORE_CTRL_STOP) = '1' then
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stopping <= '1';
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end if;
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if dmi_din(DBG_CORE_CTRL_STEP) = '1' then
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do_step <= '1';
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terminated <= '0';
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end if;
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if dmi_din(DBG_CORE_CTRL_ICRESET) = '1' then
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do_icreset <= '1';
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end if;
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if dmi_din(DBG_CORE_CTRL_START) = '1' then
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stopping <= '0';
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terminated <= '0';
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end if;
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elsif dmi_addr = DBG_CORE_GSPR_INDEX then
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gspr_index <= dmi_din(gspr_index_t'left downto 0);
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elsif dmi_addr = DBG_CORE_LOG_ADDR then
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log_dmi_addr <= dmi_din(31 downto 0);
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do_dmi_log_rd <= '1';
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end if;
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else
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report("DMI read from " & to_string(dmi_addr));
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end if;
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elsif dmi_read_log_data = '0' and dmi_read_log_data_1 = '1' then
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-- Increment log_dmi_addr after the end of a read from DBG_CORE_LOG_DATA
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log_dmi_addr(LOG_INDEX_BITS + 1 downto 0) <=
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std_ulogic_vector(unsigned(log_dmi_addr(LOG_INDEX_BITS+1 downto 0)) + 1);
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do_dmi_log_rd <= '1';
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end if;
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dmi_read_log_data_1 <= dmi_read_log_data;
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if dmi_req = '1' and dmi_addr = DBG_CORE_LOG_DATA then
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dmi_read_log_data <= '1';
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else
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dmi_read_log_data <= '0';
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end if;
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-- Set core stop on terminate. We'll be stopping some time *after*
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-- the offending instruction, at least until we can do back flushes
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-- that preserve NIA which we can't just yet.
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if terminate = '1' then
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stopping <= '1';
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terminated <= '1';
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end if;
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end if;
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end if;
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end process;
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dbg_gpr_addr <= gspr_index;
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-- Core control signals generated by the debug module
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core_stop <= stopping and not do_step;
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core_rst <= do_reset;
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icache_rst <= do_icreset;
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terminated_out <= terminated;
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-- Use MSB of read addresses to stop the logging
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log_wr_enable <= not (log_read_addr(31) or log_dmi_addr(31));
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log_ram: process(clk)
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begin
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if rising_edge(clk) then
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if log_wr_enable = '1' then
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log_array(to_integer(log_wr_ptr)) <= log_data;
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end if;
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log_rd <= log_array(to_integer(log_rd_ptr_latched));
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end if;
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end process;
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log_buffer: process(clk)
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variable b : integer;
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variable data : std_ulogic_vector(255 downto 0);
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begin
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if rising_edge(clk) then
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if rst = '1' then
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log_wr_ptr <= (others => '0');
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log_toggle <= '0';
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elsif log_wr_enable = '1' then
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if log_wr_ptr = to_unsigned(LOG_LENGTH - 1, LOG_INDEX_BITS) then
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log_toggle <= not log_toggle;
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end if;
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log_wr_ptr <= log_wr_ptr + 1;
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end if;
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if do_dmi_log_rd = '1' then
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log_rd_ptr_latched <= unsigned(log_dmi_addr(LOG_INDEX_BITS + 1 downto 2));
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else
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log_rd_ptr_latched <= unsigned(log_read_addr(LOG_INDEX_BITS + 1 downto 2));
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end if;
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if log_dmi_read_done = '1' then
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log_dmi_data <= select_dword(log_rd, log_dmi_addr);
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else
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log_read_data <= select_dword(log_rd, log_read_addr);
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end if;
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log_dmi_read_done <= log_dmi_reading;
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log_dmi_reading <= do_dmi_log_rd;
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end if;
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end process;
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log_write_addr(LOG_INDEX_BITS - 1 downto 0) <= std_ulogic_vector(log_wr_ptr);
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log_write_addr(LOG_INDEX_BITS) <= '1';
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log_write_addr(31 downto LOG_INDEX_BITS + 1) <= (others => '0');
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end behave;
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