mirror of
https://github.com/antonblanchard/microwatt.git
synced 2026-01-11 23:43:15 +00:00
bc0f7cf236
Experimenting with using ghdl to do VHDL to Verilog conversion (instead
of ghdl+yosys), verilator complains that a signal is a SystemVerilog
keyword:
%Error: microwatt.v:15013:18: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.
... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.
We could probably make this go away by disabling SystemVerilog, but
it's easy to rename the signal in question. Rename di at the same
time.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
68 lines
2.2 KiB
VHDL
68 lines
2.2 KiB
VHDL
-- Single port Block RAM with one cycle output buffer
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--
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-- Simulated via C helpers
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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use work.utils.all;
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use work.sim_bram_helpers.all;
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entity main_bram is
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generic(
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WIDTH : natural := 64;
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HEIGHT_BITS : natural := 1024;
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MEMORY_SIZE : natural := 65536;
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RAM_INIT_FILE : string
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);
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port(
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clk : in std_logic;
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addr : in std_logic_vector(HEIGHT_BITS - 1 downto 0) ;
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din : in std_logic_vector(WIDTH-1 downto 0);
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dout : out std_logic_vector(WIDTH-1 downto 0);
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sel : in std_logic_vector((WIDTH/8)-1 downto 0);
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re : in std_ulogic;
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we : in std_ulogic
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);
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end entity main_bram;
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architecture sim of main_bram is
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constant WIDTH_BYTES : natural := WIDTH / 8;
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constant pad_zeros : std_ulogic_vector(log2(WIDTH_BYTES)-1 downto 0)
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:= (others => '0');
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signal identifier : integer := behavioural_initialize(filename => RAM_INIT_FILE,
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size => MEMORY_SIZE);
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-- Others
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signal obuf : std_logic_vector(WIDTH-1 downto 0);
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begin
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-- Actual RAM template
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memory_0: process(clk)
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variable ret_dat_v : std_ulogic_vector(63 downto 0);
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variable addr64 : std_ulogic_vector(63 downto 0);
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begin
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if rising_edge(clk) then
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addr64 := (others => '0');
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addr64(HEIGHT_BITS + 2 downto 3) := addr;
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if we = '1' then
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report "RAM writing " & to_hstring(din) & " to " &
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to_hstring(addr & pad_zeros) & " sel:" & to_hstring(sel);
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behavioural_write(din, addr64, to_integer(unsigned(sel)), identifier);
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end if;
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if re = '1' then
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behavioural_read(ret_dat_v, addr64, to_integer(unsigned(sel)), identifier);
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report "RAM reading from " & to_hstring(addr & pad_zeros) &
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" returns " & to_hstring(ret_dat_v);
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obuf <= ret_dat_v(obuf'left downto 0);
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end if;
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dout <= obuf;
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end if;
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end process;
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end architecture sim;
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