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https://github.com/captain-amygdala/pistorm.git
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Added support for C1/C3 clock calculation
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11404
rtl/EPM240_bitstream.svf
11404
rtl/EPM240_bitstream.svf
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19886
rtl/bitstream.svf
19886
rtl/bitstream.svf
File diff suppressed because it is too large
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File diff suppressed because it is too large
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@ -110,10 +110,14 @@ set_location_assignment PIN_73 -to M68K_UDS_n
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set_location_assignment PIN_74 -to M68K_LDS_n
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set_location_assignment PIN_75 -to M68K_RW
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set_location_assignment PIN_76 -to M68K_DTACK_n
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set_location_assignment PIN_51 -to CLK_SEL
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set_location_assignment PIN_99 -to M68K_C1
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set_location_assignment PIN_100 -to M68K_C3
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to M68K_IPL_n[0]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to M68K_IPL_n[1]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to M68K_IPL_n[2]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to M68K_IPL_n[0]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to M68K_IPL_n[1]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to M68K_IPL_n[2]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to CLK_SEL
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set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
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set_global_assignment -name ENABLE_OCT_DONE OFF
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@ -41,7 +41,8 @@ set_time_format -unit ns -decimal_places 3
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create_clock -name {PI_CLK} -period 5.000 [get_ports {PI_CLK}]
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create_clock -name {M68K_CLK} -period 141.000 [get_ports {M68K_CLK}]
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create_clock -name {M68K_C1} -period 282.000 [get_ports {M68K_C1}]
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create_clock -name {M68K_C3} -period 282.000 [get_ports {M68K_C3}]
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#**************************************************************
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# Create Generated Clock
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@ -46,13 +46,17 @@ module pistorm(
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input M68K_BR_n,
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output reg M68K_BG_n,
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input M68K_BGACK_n
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input M68K_BGACK_n,
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input M68K_C1,
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input M68K_C3,
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input CLK_SEL
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);
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wire c200m = PI_CLK;
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reg [2:0] c7m_sync;
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// wire c7m = M68K_CLK;
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wire c7m = c7m_sync[2];
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wire c1c3_clk = !(M68K_C1 ^ M68K_C3);
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localparam REG_DATA = 2'd0;
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localparam REG_ADDR_LO = 2'd1;
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@ -122,7 +126,7 @@ module pistorm(
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reg a0;
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always @(posedge c200m) begin
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c7m_sync <= {c7m_sync[1:0], M68K_CLK};
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c7m_sync <= {c7m_sync[1:0], (CLK_SEL?M68K_CLK:c1c3_clk)};
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end
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wire c7m_rising = !c7m_sync[2] && c7m_sync[1];
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