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Some stability improvements for Chip fastpath?

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This commit is contained in:
beeanyew
2021-08-10 15:41:00 +02:00
parent 9043334114
commit 88c8b9d47c
2 changed files with 31 additions and 2 deletions
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13
gpio/ps_protocol.c
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@@ -232,7 +232,10 @@ void ps_write_status_reg(unsigned int value) {
*(gpio + 7) = ((value & 0xffff) << 8) | (REG_STATUS << PIN_A0);
*(gpio + 7) = 1 << PIN_WR;
*(gpio + 7) = 1 << PIN_WR; // delay
*(gpio + 7) = 1 << PIN_WR; // delay
#ifdef CHIP_FASTPATH
*(gpio + 7) = 1 << PIN_WR; // delay 210810
#endif
*(gpio + 10) = 1 << PIN_WR;
*(gpio + 10) = 0xffffec;
@@ -247,9 +250,14 @@ unsigned int ps_read_status_reg() {
*(gpio + 7) = 1 << PIN_RD;
*(gpio + 7) = 1 << PIN_RD;
*(gpio + 7) = 1 << PIN_RD;
#ifdef CHIP_FASTPATH
*(gpio + 7) = 1 << PIN_RD; // delay 210810
*(gpio + 7) = 1 << PIN_RD; // delay 210810
#endif
unsigned int value = *(gpio + 13);
while ((value=*(gpio + 13)) & (1 << PIN_TXN_IN_PROGRESS)) {}
*(gpio + 10) = 0xffffec;
return (value >> 8) & 0xffff;
@@ -270,6 +278,7 @@ void ps_pulse_reset() {
unsigned int ps_get_ipl_zero() {
unsigned int value = *(gpio + 13);
while ((value=*(gpio + 13)) & (1 << PIN_TXN_IN_PROGRESS)) {}
return value & (1 << PIN_IPL_ZERO);
}