5 Commits

Author	SHA1	Message	Date
beeanyew	bab7a847c0	Make experimental bitstream optional	2021-06-20 16:59:11 +01:00
shanshe	d602910beb	Improve 68k cycle state machine ... S7 and S0 states are made faster to gain almost a c7m cycle, making Chip access faster. (sysinfo 4.4 chip speed from 0.97 to 1.13)	2021-06-18 11:48:45 +02:00
shanshe	75bbc70be8	Reset from Amiga CTRL+A+A	2021-04-13 21:53:44 +02:00
beeanyew	1f804c7e36	[WIP] IRQ experiments, revert Musashi speed hax for now	2021-03-08 15:53:23 +01:00
beeanyew	e764148bb1	[WIP] Pile of stuff ... PiSCSI Boot ROM progress, various fixes and enhancements, TD64 support Added updated open source RTL and bit stream by Niklas Ekström (https://github.com/niklasekstrom)	2021-02-10 08:33:52 +01:00