6 Commits

Author	SHA1	Message	Date
Claude	d1ec44a9e6	bus timing back to normal, 68k data sampling point 2 cycles earlier	2020-11-23 16:34:24 +00:00
Claude	cba527e2af	FPGA 68k bus write and read a bit later in SMI statemachine	2020-11-23 16:08:34 +00:00
Claude	33493e87dc	IDE IRQ, FPGA with maximum current strength on FET busctrl signals	2020-11-23 15:55:04 +00:00
Claude	cbb5f0fd6d	bus access a bit optimized	2020-11-22 11:41:07 +00:00
Claude	f2baf55223	reset handling, fpga update needed	2020-11-22 08:55:42 +00:00
Claude	87786b6976	fixed mmu and fpu detection, added reset handling for autoconf, added fpga update	2020-11-21 10:12:43 +00:00