mirror of
https://github.com/captain-amygdala/pistorm.git
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292 lines
7.1 KiB
C
292 lines
7.1 KiB
C
// SPDX-License-Identifier: MIT
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/*
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Original Copyright 2020 Claude Schwarz
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Code reorganized and rewritten by
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Niklas Ekström 2021 (https://github.com/niklasekstrom)
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*/
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#include <errno.h>
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#include <fcntl.h>
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#include <stddef.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <sys/mman.h>
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#include <sys/stat.h>
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#include <sys/types.h>
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#include <unistd.h>
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#include "ps_protocol.h"
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#include "m68k.h"
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volatile unsigned int *gpio;
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volatile unsigned int *gpclk;
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unsigned int gpfsel0;
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unsigned int gpfsel1;
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unsigned int gpfsel2;
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unsigned int gpfsel0_o;
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unsigned int gpfsel1_o;
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unsigned int gpfsel2_o;
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static void setup_io() {
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int fd = open("/dev/mem", O_RDWR | O_SYNC);
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if (fd < 0) {
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printf("Unable to open /dev/mem. Run as root using sudo?\n");
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exit(-1);
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}
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void *gpio_map = mmap(
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NULL, // Any adddress in our space will do
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BCM2708_PERI_SIZE, // Map length
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PROT_READ | PROT_WRITE, // Enable reading & writting to mapped memory
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MAP_SHARED, // Shared with other processes
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fd, // File to map
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BCM2708_PERI_BASE // Offset to GPIO peripheral
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);
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close(fd);
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if (gpio_map == MAP_FAILED) {
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printf("mmap failed, errno = %d\n", errno);
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exit(-1);
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}
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gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR / 4;
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gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR / 4;
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}
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static void setup_gpclk() {
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// Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending
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// on pi model
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*(gpclk + (CLK_GP0_CTL / 4)) = CLK_PASSWD | (1 << 5);
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usleep(10);
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while ((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7))
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;
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usleep(100);
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*(gpclk + (CLK_GP0_DIV / 4)) =
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CLK_PASSWD | (6 << 12); // divider , 6=200MHz on pi3
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usleep(10);
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*(gpclk + (CLK_GP0_CTL / 4)) =
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CLK_PASSWD | 5 | (1 << 4); // pll? 6=plld, 5=pllc
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usleep(10);
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while (((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7)) == 0)
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;
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usleep(100);
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SET_GPIO_ALT(PIN_CLK, 0); // gpclk0
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}
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void ps_setup_protocol() {
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setup_io();
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setup_gpclk();
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*(gpio + 10) = 0xffffec;
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*(gpio + 0) = GPFSEL0_INPUT;
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*(gpio + 1) = GPFSEL1_INPUT;
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*(gpio + 2) = GPFSEL2_INPUT;
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}
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void ps_write_16(unsigned int address, unsigned int data) {
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*(gpio + 0) = GPFSEL0_OUTPUT;
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*(gpio + 1) = GPFSEL1_OUTPUT;
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*(gpio + 2) = GPFSEL2_OUTPUT;
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*(gpio + 7) = ((data & 0xffff) << 8) | (REG_DATA << PIN_A0);
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*(gpio + 7) = 1 << PIN_WR;
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*(gpio + 10) = 1 << PIN_WR;
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*(gpio + 10) = 0xffffec;
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*(gpio + 7) = ((address & 0xffff) << 8) | (REG_ADDR_LO << PIN_A0);
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*(gpio + 7) = 1 << PIN_WR;
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*(gpio + 10) = 1 << PIN_WR;
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*(gpio + 10) = 0xffffec;
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*(gpio + 7) = ((0x0000 | (address >> 16)) << 8) | (REG_ADDR_HI << PIN_A0);
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*(gpio + 7) = 1 << PIN_WR;
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*(gpio + 10) = 1 << PIN_WR;
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*(gpio + 10) = 0xffffec;
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*(gpio + 0) = GPFSEL0_INPUT;
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*(gpio + 1) = GPFSEL1_INPUT;
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*(gpio + 2) = GPFSEL2_INPUT;
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while (*(gpio + 13) & (1 << PIN_TXN_IN_PROGRESS)) {}
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}
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void ps_write_8(unsigned int address, unsigned int data) {
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if ((address & 1) == 0)
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data = data + (data << 8); // EVEN, A0=0,UDS
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else
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data = data & 0xff; // ODD , A0=1,LDS
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*(gpio + 0) = GPFSEL0_OUTPUT;
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*(gpio + 1) = GPFSEL1_OUTPUT;
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*(gpio + 2) = GPFSEL2_OUTPUT;
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*(gpio + 7) = ((data & 0xffff) << 8) | (REG_DATA << PIN_A0);
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*(gpio + 7) = 1 << PIN_WR;
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*(gpio + 10) = 1 << PIN_WR;
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*(gpio + 10) = 0xffffec;
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*(gpio + 7) = ((address & 0xffff) << 8) | (REG_ADDR_LO << PIN_A0);
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*(gpio + 7) = 1 << PIN_WR;
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*(gpio + 10) = 1 << PIN_WR;
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*(gpio + 10) = 0xffffec;
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*(gpio + 7) = ((0x0100 | (address >> 16)) << 8) | (REG_ADDR_HI << PIN_A0);
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*(gpio + 7) = 1 << PIN_WR;
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*(gpio + 10) = 1 << PIN_WR;
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*(gpio + 10) = 0xffffec;
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*(gpio + 0) = GPFSEL0_INPUT;
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*(gpio + 1) = GPFSEL1_INPUT;
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*(gpio + 2) = GPFSEL2_INPUT;
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while (*(gpio + 13) & (1 << PIN_TXN_IN_PROGRESS)) {}
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}
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void ps_write_32(unsigned int address, unsigned int value) {
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ps_write_16(address, value >> 16);
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ps_write_16(address + 2, value);
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}
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unsigned int ps_read_16(unsigned int address) {
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*(gpio + 0) = GPFSEL0_OUTPUT;
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*(gpio + 1) = GPFSEL1_OUTPUT;
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*(gpio + 2) = GPFSEL2_OUTPUT;
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*(gpio + 7) = ((address & 0xffff) << 8) | (REG_ADDR_LO << PIN_A0);
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*(gpio + 7) = 1 << PIN_WR;
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*(gpio + 10) = 1 << PIN_WR;
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*(gpio + 10) = 0xffffec;
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*(gpio + 7) = ((0x0200 | (address >> 16)) << 8) | (REG_ADDR_HI << PIN_A0);
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*(gpio + 7) = 1 << PIN_WR;
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*(gpio + 10) = 1 << PIN_WR;
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*(gpio + 10) = 0xffffec;
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*(gpio + 0) = GPFSEL0_INPUT;
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*(gpio + 1) = GPFSEL1_INPUT;
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*(gpio + 2) = GPFSEL2_INPUT;
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*(gpio + 7) = (REG_DATA << PIN_A0);
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*(gpio + 7) = 1 << PIN_RD;
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while (*(gpio + 13) & (1 << PIN_TXN_IN_PROGRESS)) {}
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unsigned int value = *(gpio + 13);
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*(gpio + 10) = 0xffffec;
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return (value >> 8) & 0xffff;
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}
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unsigned int ps_read_8(unsigned int address) {
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*(gpio + 0) = GPFSEL0_OUTPUT;
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*(gpio + 1) = GPFSEL1_OUTPUT;
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*(gpio + 2) = GPFSEL2_OUTPUT;
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*(gpio + 7) = ((address & 0xffff) << 8) | (REG_ADDR_LO << PIN_A0);
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*(gpio + 7) = 1 << PIN_WR;
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*(gpio + 10) = 1 << PIN_WR;
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*(gpio + 10) = 0xffffec;
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*(gpio + 7) = ((0x0300 | (address >> 16)) << 8) | (REG_ADDR_HI << PIN_A0);
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*(gpio + 7) = 1 << PIN_WR;
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*(gpio + 10) = 1 << PIN_WR;
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*(gpio + 10) = 0xffffec;
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*(gpio + 0) = GPFSEL0_INPUT;
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*(gpio + 1) = GPFSEL1_INPUT;
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*(gpio + 2) = GPFSEL2_INPUT;
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*(gpio + 7) = (REG_DATA << PIN_A0);
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*(gpio + 7) = 1 << PIN_RD;
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while (*(gpio + 13) & (1 << PIN_TXN_IN_PROGRESS)) {}
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unsigned int value = *(gpio + 13);
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*(gpio + 10) = 0xffffec;
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value = (value >> 8) & 0xffff;
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if ((address & 1) == 0)
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return (value >> 8) & 0xff; // EVEN, A0=0,UDS
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else
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return value & 0xff; // ODD , A0=1,LDS
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}
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unsigned int ps_read_32(unsigned int address) {
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unsigned int a = ps_read_16(address);
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unsigned int b = ps_read_16(address + 2);
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return (a << 16) | b;
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}
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void ps_write_status_reg(unsigned int value) {
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*(gpio + 0) = GPFSEL0_OUTPUT;
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*(gpio + 1) = GPFSEL1_OUTPUT;
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*(gpio + 2) = GPFSEL2_OUTPUT;
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*(gpio + 7) = ((value & 0xffff) << 8) | (REG_STATUS << PIN_A0);
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*(gpio + 7) = 1 << PIN_WR;
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*(gpio + 7) = 1 << PIN_WR; // delay
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*(gpio + 10) = 1 << PIN_WR;
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*(gpio + 10) = 0xffffec;
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*(gpio + 0) = GPFSEL0_INPUT;
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*(gpio + 1) = GPFSEL1_INPUT;
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*(gpio + 2) = GPFSEL2_INPUT;
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}
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unsigned int ps_read_status_reg() {
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*(gpio + 7) = (REG_STATUS << PIN_A0);
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*(gpio + 7) = 1 << PIN_RD;
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*(gpio + 7) = 1 << PIN_RD;
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*(gpio + 7) = 1 << PIN_RD;
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*(gpio + 7) = 1 << PIN_RD;
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unsigned int value = *(gpio + 13);
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*(gpio + 10) = 0xffffec;
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return (value >> 8) & 0xffff;
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}
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void ps_reset_state_machine() {
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ps_write_status_reg(STATUS_BIT_INIT);
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usleep(1500);
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ps_write_status_reg(0);
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usleep(100);
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}
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void ps_pulse_reset() {
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ps_write_status_reg(0);
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usleep(100000);
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ps_write_status_reg(STATUS_BIT_RESET);
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}
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unsigned int ps_get_ipl_zero() {
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unsigned int value = *(gpio + 13);
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return value & (1 << PIN_IPL_ZERO);
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}
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#define INT2_ENABLED 1
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void ps_update_irq() {
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unsigned int ipl = 0;
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if (!ps_get_ipl_zero()) {
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unsigned int status = ps_read_status_reg();
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ipl = (status & 0xe000) >> 13;
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}
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/*if (ipl < 2 && INT2_ENABLED && emu_int2_req()) {
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ipl = 2;
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}*/
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m68k_set_irq(ipl);
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}
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