mirror of
https://github.com/chip-red-pill/uCodeDisasm.git
synced 2026-01-11 23:53:26 +00:00
5b2b1f1246
2. Secure Enclave (SGX) SVN key generation is found 3. A Python module is implemented for the disassembler 4. Many other microarchitectural data are found and added
651 lines
14 KiB
Plaintext
651 lines
14 KiB
Plaintext
000: ADD_DSZ32
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001: OR_DSZ32
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004: AND_DSZ32
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005: SUB_DSZ32
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006: XOR_DSZ32
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007: NOTAND_DSZ32
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008: ZEROEXT_DSZ32
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009: MOVE_DSZ32
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00a: TESTUSTATE
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00b: UPDATEUSTATE
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00c: SAVEUIP
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00d: SAVEUIP_REGOVR
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00e: WRMSLOOPCTRFBR
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014: BT_DSZ32
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015: BTS_DSZ32
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016: BTR_DSZ32
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017: BTC_DSZ32
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01e: MJMPTARGET_INDIRECT_ASZ32
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021: CONCAT_DSZ32
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024: SHL_DSZ32
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025: SHR_DSZ32
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02c: ROL_DSZ32
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02d: ROR_DSZ32
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02e: SAR_DSZ32
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030: SELECTCC_DSZ32_CONDO
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031: SELECTCC_DSZ32_CONDNO
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032: SELECTCC_DSZ32_CONDB
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033: SELECTCC_DSZ32_CONDNB
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034: CMOVCC_DSZ32_CONDO
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035: CMOVCC_DSZ32_CONDNO
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036: CMOVCC_DSZ32_CONDB
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037: CMOVCC_DSZ32_CONDNB
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03d: MOVEINSERTFLGS_DSZ32
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040: ADD_DSZ64
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041: OR_DSZ64
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042: MOVETOCREG_DSZ64
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043: WRITEURAM
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044: AND_DSZ64
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045: SUB_DSZ64
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046: XOR_DSZ64
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047: NOTAND_DSZ64
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048: ZEROEXT_DSZ64
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049: MOVE_DSZ64
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04a: TESTUSTATE
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04c: SAVEUIP
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04d: SAVEUIP_REGOVR
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050: UJMPCC_DIRECT_NOTTAKEN_CONDO
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051: UJMPCC_DIRECT_NOTTAKEN_CONDNO
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052: UJMPCC_DIRECT_NOTTAKEN_CONDB
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053: UJMPCC_DIRECT_NOTTAKEN_CONDNB
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054: BT_DSZ64
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055: BTS_DSZ64
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056: BTR_DSZ64
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057: BTC_DSZ64
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058: MJMPCC_DSZNOP_CONDO
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059: MJMPCC_DSZNOP_CONDNO
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05a: MJMPCC_DSZNOP_CONDB
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05b: MJMPCC_DSZNOP_CONDNB
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05c: MJMPTARGET_INDIRECT_ASZ64
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05e: MJMPTARGET_INDIRECT_ASZ64
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062: MOVEFROMCREG_DSZ64
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063: READURAM
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064: SHL_DSZ64
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065: SHR_DSZ64
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06c: ROL_DSZ64
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06d: ROR_DSZ64
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06e: SAR_DSZ64
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070: SELECTCC_DSZ64_CONDO
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071: SELECTCC_DSZ64_CONDNO
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072: SELECTCC_DSZ64_CONDB
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073: SELECTCC_DSZ64_CONDNB
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074: CMOVCC_DSZ64_CONDO
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075: CMOVCC_DSZ64_CONDNO
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076: CMOVCC_DSZ64_CONDB
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077: CMOVCC_DSZ64_CONDNB
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07d: MOVEINSERTFLGS_DSZ64
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080: ADD_DSZ16
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081: OR_DSZ16
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084: AND_DSZ16
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085: SUB_DSZ16
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086: XOR_DSZ16
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087: NOTAND_DSZ16
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088: ZEROEXT_DSZ16
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08c: SAVEUIP
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094: BT_DSZ16
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095: BTS_DSZ16
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096: BTR_DSZ16
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097: BTC_DSZ16
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0a1: CONCAT_DSZ16
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0a4: SHL_DSZ16
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0a5: SHR_DSZ16
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0a8: MOVSX_DSZ16
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0a9: MOVZX_DSZ16
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0ac: ROL_DSZ16
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0ad: ROR_DSZ16
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0ae: SAR_DSZ16
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0b4: CMOVCC_DSZ16_CONDO
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0b5: CMOVCC_DSZ16_CONDNO
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0b6: CMOVCC_DSZ16_CONDB
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0b7: CMOVCC_DSZ16_CONDNB
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0c0: ADD_DSZ8
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0c1: OR_DSZ8
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0c4: AND_DSZ8
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0c5: SUB_DSZ8
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0c6: XOR_DSZ8
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0c7: NOTAND_DSZ8
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0c8: ZEROEXT_DSZ8
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0cc: SAVEUIP
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0e0: NEG_DSZ8
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0e1: CONCAT_DSZ8
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0e4: SHL_DSZ8
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0e5: SHR_DSZ8
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0e8: MOVSX_DSZ8
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0e9: MOVZX_DSZ8
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0ec: ROL_DSZ8
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0ed: ROR_DSZ8
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0ee: SAR_DSZ8
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0f4: CMOVCC_DSZ8_CONDO
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0f5: CMOVCC_DSZ8_CONDNO
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0f6: CMOVCC_DSZ8_CONDB
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0f7: CMOVCC_DSZ8_CONDNB
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0f8: SETCC_CONDO
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0f9: SETCC_CONDNO
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0fa: SETCC_CONDB
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0fb: SETCC_CONDNB
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108: READUIP_REGOVR
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120: SUBR_DSZ32
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122: RCXBTCNTMSK_DSZ32
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130: SELECTCC_DSZ32_CONDNZ
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131: SELECTCC_DSZ32_CONDZ
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132: SELECTCC_DSZ32_CONDBE
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133: SELECTCC_DSZ32_CONDNBE
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134: CMOVCC_DSZ32_CONDZ
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135: CMOVCC_DSZ32_CONDNZ
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136: CMOVCC_DSZ32_CONDBE
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137: CMOVCC_DSZ32_CONDNBE
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13e: MOVEMERGEFLGS_DSZ32
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142: UFLOWCTRL
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143: AETTRACE
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148: URET
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150: UJMPCC_DIRECT_NOTTAKEN_CONDZ
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151: UJMPCC_DIRECT_NOTTAKEN_CONDNZ
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152: UJMPCC_DIRECT_NOTTAKEN_CONDBE
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153: UJMPCC_DIRECT_NOTTAKEN_CONDNBE
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158: MJMPCC_DSZNOP_CONDZ
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159: MJMPCC_DSZNOP_CONDNZ
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15a: MJMPCC_DSZNOP_CONDBE
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15b: MJMPCC_DSZNOP_CONDNBE
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15d: UJMP
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15f: UJMPCC_DIRECT_TAKEN_CONDZ
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160: SUBR_DSZ64
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162: RCXBTCNTMSK_DSZ64
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170: SELECTCC_DSZ64_CONDNZ
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171: SELECTCC_DSZ64_CONDZ
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172: SELECTCC_DSZ64_CONDBE
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173: SELECTCC_DSZ64_CONDNBE
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174: CMOVCC_DSZ64_CONDZ
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175: CMOVCC_DSZ64_CONDNZ
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176: CMOVCC_DSZ64_CONDBE
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177: CMOVCC_DSZ64_CONDNBE
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17e: MOVEMERGEFLGS_DSZ64
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189: ADDSUB_DSZ16_CONDD
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1a0: SUBR_DSZ16
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1a2: RCXBTCNTMSK_DSZ16
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1b4: CMOVCC_DSZ16_CONDZ
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1b5: CMOVCC_DSZ16_CONDNZ
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1b6: CMOVCC_DSZ16_CONDBE
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1b7: CMOVCC_DSZ16_CONDNBE
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1bf: SAHF
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1e0: SUBR_DSZ8
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1e2: RCXBTCNTMSK_DSZ8
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1f4: CMOVCC_DSZ8_CONDZ
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1f5: CMOVCC_DSZ8_CONDNZ
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1f6: CMOVCC_DSZ8_CONDBE
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1f7: CMOVCC_DSZ8_CONDNBE
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1f8: SETCC_CONDZ
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1f9: SETCC_CONDNZ
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1fa: SETCC_CONDBE
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1fb: SETCC_CONDNBE
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202: PSELECT_CPL0
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214: FETCHFROMEIP0_ASZ32
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215: FETCHFROMEIP1_ASZ32
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21e: SIGEVENT
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225: IMUL32L_DSZ32
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228: MSR2CR
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22c: MUL_DSZ32
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22d: IMUL_DSZ32
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230: SELECTCC_DSZ32_CONDS
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231: SELECTCC_DSZ32_CONDNS
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232: SELECTCC_DSZ32_CONDP
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233: SELECTCC_DSZ32_CONDNP
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234: CMOVCC_DSZ32_CONDS
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235: CMOVCC_DSZ32_CONDNS
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236: CMOVCC_DSZ32_CONDP
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237: CMOVCC_DSZ32_CONDNP
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250: UJMPCC_DIRECT_NOTTAKEN_CONDS
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251: UJMPCC_DIRECT_NOTTAKEN_CONDNS
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252: UJMPCC_DIRECT_NOTTAKEN_CONDP
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253: UJMPCC_DIRECT_NOTTAKEN_CONDNP
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254: FETCHFROMEIP0_ASZ64
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255: FETCHFROMEIP1_ASZ64
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258: MJMPCC_DSZNOP_CONDS
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259: MJMPCC_DSZNOP_CONDNS
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25a: MJMPCC_DSZNOP_CONDP
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25b: MJMPCC_DSZNOP_CONDNP
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25d: TEST_DSZ64
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264: IMUL64L_DSZ64
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269: RDVMCSPLA
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270: SELECTCC_DSZ64_CONDS
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271: SELECTCC_DSZ64_CONDNS
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272: SELECTCC_DSZ64_CONDP
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273: SELECTCC_DSZ64_CONDNP
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274: CMOVCC_DSZ64_CONDS
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275: CMOVCC_DSZ64_CONDNS
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276: CMOVCC_DSZ64_CONDP
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277: CMOVCC_DSZ64_CONDNP
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2b4: CMOVCC_DSZ16_CONDS
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2b5: CMOVCC_DSZ16_CONDNS
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2b6: CMOVCC_DSZ16_CONDP
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2b7: CMOVCC_DSZ16_CONDNP
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2f4: CMOVCC_DSZ8_CONDS
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2f5: CMOVCC_DSZ8_CONDNS
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2f6: CMOVCC_DSZ8_CONDP
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2f7: CMOVCC_DSZ8_CONDNP
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2f8: SETCC_CONDS
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2f9: SETCC_CONDNS
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2fa: SETCC_CONDP
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2fb: SETCC_CONDNP
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32e: RCL_DSZ32
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330: SELECTCC_DSZ32_CONDL
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331: SELECTCC_DSZ32_CONDNL
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332: SELECTCC_DSZ32_CONDLE
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333: SELECTCC_DSZ32_CONDNLE
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334: CMOVCC_DSZ32_CONDL
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335: CMOVCC_DSZ32_CONDNL
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336: CMOVCC_DSZ32_CONDLE
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337: CMOVCC_DSZ32_CONDNLE
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338: CLC
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339: CMC
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33a: STC
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33c: BSWAP_DSZ32
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33e: ADC
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33f: SBB
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350: UJMPCC_DIRECT_NOTTAKEN_CONDL
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351: UJMPCC_DIRECT_NOTTAKEN_CONDNL
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352: UJMPCC_DIRECT_NOTTAKEN_CONDLE
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353: UJMPCC_DIRECT_NOTTAKEN_CONDNLE
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358: MJMPCC_DSZNOP_CONDL
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359: MJMPCC_DSZNOP_CONDNL
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35a: MJMPCC_DSZNOP_CONDLE
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35b: MJMPCC_DSZNOP_CONDNLE
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370: SELECTCC_DSZ64_CONDL
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371: SELECTCC_DSZ64_CONDNL
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372: SELECTCC_DSZ64_CONDLE
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373: SELECTCC_DSZ64_CONDNLE
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374: CMOVCC_DSZ64_CONDL
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375: CMOVCC_DSZ64_CONDNL
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376: CMOVCC_DSZ64_CONDLE
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377: CMOVCC_DSZ64_CONDNLE
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37d: GENARITHFLAGS
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380: READAFLAGS
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3ae: RCL_DSZ16
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3b4: CMOVCC_DSZ16_CONDL
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3b5: CMOVCC_DSZ16_CONDNL
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3b6: CMOVCC_DSZ16_CONDLE
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3b7: CMOVCC_DSZ16_CONDNLE
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3c0: LAHF
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3c8: INC_DSZ8
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3ca: DEC_DSZ8
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3ee: RCL_DSZ8
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3f4: CMOVCC_DSZ8_CONDL
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3f5: CMOVCC_DSZ8_CONDNL
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3f6: CMOVCC_DSZ8_CONDLE
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3f7: CMOVCC_DSZ8_CONDNLE
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3f8: SETCC_CONDL
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3f9: SETCC_CONDNL
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3fa: SETCC_CONDLE
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3fb: SETCC_CONDNLE
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3fe: ADC
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3ff: SBB
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440: PSUBSB
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441: PSUBSW
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442: PMINSW
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443: POR
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444: PADDSB
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445: PADDSW
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446: PMAXSW
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447: PXOR
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448: PSUBB
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449: PSUBW
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44a: PSUBD
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44c: PADDB
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44d: PADDW
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44e: PADDD
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450: PCMPGTB
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451: PCMPGTW
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452: PCMPGTD
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457: PALIGNR
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458: PCMPEQW
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459: PCMPEQB
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45a: PCMPEQD
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45b: PADDQ
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45f: PSUBQ
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460: PSUBUSB
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461: PSUBUSW
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462: PMINUB
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463: PAND
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464: PADDUSB
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465: PADDUSW
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466: PMAXUB
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467: PANDN
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468: PAVGB
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46b: PAVGW
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470: MOVLPD
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471: MOVHPD
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472: MOVDQU
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477: PINTSLLDQQ
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4b4: FMOV
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4c3: ORPD
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4c7: PINTPXORD
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4e3: ANDPD
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4e7: ANDNPD
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4ec: PINTSRLDQ
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4ef: MOVHLPS
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508: PUNPCKLDQ
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50a: PSRLQ
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50e: PSLLQ
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514: CVTPD2PI
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518: PUNPCKHDQ
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51a: PSRLQ
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51d: PACKSSDW
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51e: PSLLQ
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528: UNPCKHPD
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529: UNPCKLPD
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556: PMADDWD
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557: PSADBW
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571: CVTPD2PS
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588: PUNPCKLWD
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58a: PSRLD
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58c: PSRAD
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58e: PSLLD
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594: CVTTPD2PI
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598: PUNPCKHWD
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59a: PSRLD
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59b: PSHUFD
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59c: PSRAD
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59d: PACKSSWB
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59e: PSLLD
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59f: PACKUSWB
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5c8: PUNPCKLBW
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5ca: PSRLW
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5cc: PSRAW
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5ce: PSLLW
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5d8: PUNPCKHBW
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5da: PSRLW
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5dc: PSRAW
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5de: PSLLW
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5f3: CVTDQ2PS
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5f5: CVTPI2PD
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5f9: MOVUPD
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5fa: SHUFPD
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608: FADDP
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646: FDIV
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650: PMULUDQ
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652: PMULHUW
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654: PMULLW
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655: PMULHW
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685: FILD
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68a: FCOM2
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6e2: AESKEYGENASSIST
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6f1: MULPD
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6f5: SQRTPD
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6f6: DIVPD
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6f8: ADDPD
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6fc: SUBPD
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6fd: MINPD
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6fe: CMPPD
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6ff: MAXPD
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705: PINTMOVDI2MM_DSZ32
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716: FPREADROM_DTYPENOP
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720: FCOMIP
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722: COMISD
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723: UCOMISD
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72c: PINTMOVDTMM2I_DSZ32
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72d: PINTMOVDMM2I_DSZ32
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745: PINTMOVDI2MM_DSZ64
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746: PINTMOVQI2XMMHQ_DSZ64
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747: PINTMOVQI2XMMLQ_DSZ64
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769: PMOVMSKB
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76c: PINTMOVDTMM2I_DSZ64
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76d: PINTMOVDMM2I_DSZ64
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76f: PINTMOVQXMMLQ2I_DSZ64
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785: PINSRW
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7ad: PEXTRW
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7b8: RSQRTPS
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7c8: AESENC
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7c9: AESENCLAST
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7ed: FCMOVNE
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7f8: MOVMSKPD
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81f: LA2LIN_DSZ32
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822: MOVETOCREG_AND_DSZ64
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86a: BTUJB_DIRECT_NOTTAKEN
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86b: BTUJNB_DIRECT_NOTTAKEN
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89f: LA2LIN_DSZ64
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8a2: MOVETOCREG_SHL_DSZ64
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902: MOVETOCREG_OR_DSZ64
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928: CMPUJZ_DIRECT_NOTTAKEN
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929: CMPUJNZ_DIRECT_NOTTAKEN
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962: MOVETOCREG_BTS_DSZ64
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9a2: MOVETOCREG_SHR_DSZ64
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996: SHLD
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997: SHRD
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a62: MOVETOCREG_BTR_DSZ64
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c00: LDZX_DSZ32_ASZ32_SC1
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c03: LEA_DSZ32_ASZ32_SC1
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c08: STAD_DSZ32_ASZ32_SC1
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c09: STADTICKLE_DSZ32_ASZ32_SC1
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c0a: LDTICKLE_DSZ32_ASZ32_SC1
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c0e: MOVNTPD
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c10: LDZX_DSZ32_ASZ32_SC1
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c13: LEA_DSZ32_ASZ32_SC1
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c18: STAD_DSZ32_ASZ32_SC1
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c19: STADTICKLE_DSZ32_ASZ32_SC1
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c1a: LDTICKLE_DSZ32_ASZ32_SC1
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c2e: MOVHPD
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c30: LDZX_DSZ32_ASZ32_SC1
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c33: LEA_DSZ32_ASZ32_SC1
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c38: STAD_DSZ32_ASZ32_SC1
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c39: STADTICKLE_DSZ32_ASZ32_SC1
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c3a: LDTICKLE_DSZ32_ASZ32_SC1
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c40: LDZX_DSZ64_ASZ32_SC1
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c43: LEA_DSZ64_ASZ32_SC1
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c48: STAD_DSZ64_ASZ32_SC1
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c49: STADTICKLE_DSZ64_ASZ32_SC1
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c4a: LDTICKLE_DSZ64_ASZ32_SC1
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c4b: RDSEGFLD
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c50: LDZX_DSZ64_ASZ32_SC1
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c53: LEA_DSZ64_ASZ32_SC1
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c58: STAD_DSZ64_ASZ32_SC1
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c59: STADTICKLE_DSZ64_ASZ32_SC1
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c5a: LDTICKLE_DSZ64_ASZ32_SC1
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c5e: MOVLPD
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c6b: WRSEGFLD
|
|
c70: LDZX_DSZ64_ASZ32_SC1
|
|
c73: LEA_DSZ64_ASZ32_SC1
|
|
c78: STAD_DSZ64_ASZ32_SC1
|
|
c79: STADTICKLE_DSZ64_ASZ32_SC1
|
|
c7a: LDTICKLE_DSZ64_ASZ32_SC1
|
|
c7b: WRSEGFLD
|
|
c80: LDZX_DSZ16_ASZ32_SC1
|
|
c83: LEA_DSZ16_ASZ32_SC1
|
|
c88: STAD_DSZ16_ASZ32_SC1
|
|
c89: STADTICKLE_DSZ16_ASZ32_SC1
|
|
c8a: LDTICKLE_DSZ16_ASZ32_SC1
|
|
c90: LDZX_DSZ16_ASZ32_SC1
|
|
c93: LEA_DSZ16_ASZ32_SC1
|
|
c98: STAD_DSZ16_ASZ32_SC1
|
|
c99: STADTICKLE_DSZ16_ASZ32_SC1
|
|
c9a: LDTICKLE_DSZ16_ASZ32_SC1
|
|
cb0: LDZX_DSZ16_ASZ32_SC1
|
|
cb3: LEA_DSZ16_ASZ32_SC1
|
|
cb8: STAD_DSZ16_ASZ32_SC1
|
|
cb9: STADTICKLE_DSZ16_ASZ32_SC1
|
|
cba: LDTICKLE_DSZ16_ASZ32_SC1
|
|
cbe: MOVNTDQ
|
|
cc0: LDZX_DSZ8_ASZ32_SC1
|
|
ccf: LEA_DSZ8_ASZ32_SC1
|
|
cc8: STAD_DSZ8_ASZ32_SC1
|
|
cc9: STADTICKLE_DSZ8_ASZ32_SC1
|
|
cca: LDTICKLE_DSZ8_ASZ32_SC1
|
|
cd0: LDZX_DSZ8_ASZ32_SC1
|
|
cd3: LEA_DSZ8_ASZ32_SC1
|
|
cd8: STAD_DSZ8_ASZ32_SC1
|
|
cd9: STADTICKLE_DSZ8_ASZ32_SC1
|
|
cda: LDTICKLE_DSZ8_ASZ32_SC1
|
|
cf0: LDZX_DSZ8_ASZ32_SC1
|
|
cf3: LEA_DSZ8_ASZ32_SC1
|
|
cf5: LDHINT_BUFFER_ASZ32_SC1
|
|
cf8: STAD_DSZ8_ASZ32_SC1
|
|
cf9: STADTICKLE_DSZ8_ASZ32_SC1
|
|
cfa: LDTICKLE_DSZ8_ASZ32_SC1
|
|
cfe: MASKMOVDQU
|
|
d00: LDZX_DSZ32_ASZ32_SC4
|
|
d03: LEA_DSZ32_ASZ32_SC4
|
|
d08: STAD_DSZ32_ASZ32_SC4
|
|
d09: STADTICKLE_DSZ32_ASZ32_SC4
|
|
d0a: LDTICKLE_DSZ32_ASZ32_SC4
|
|
d0b: PORTIN_DSZ32_ASZ16_SC1
|
|
d0f: PORTOUT_DSZ32_ASZ16_SC1
|
|
d10: LDZX_DSZ32_ASZ32_SC4
|
|
d13: LEA_DSZ32_ASZ32_SC4
|
|
d18: STAD_DSZ32_ASZ32_SC4
|
|
d19: STADTICKLE_DSZ32_ASZ32_SC4
|
|
d1a: LDTICKLE_DSZ32_ASZ32_SC4
|
|
d30: LDZX_DSZ32_ASZ32_SC1
|
|
d33: LEA_DSZ32_ASZ32_SC1
|
|
d38: STAD_DSZ32_ASZ32_SC1
|
|
d39: STADTICKLE_DSZ32_ASZ32_SC1
|
|
d3a: LDTICKLE_DSZ32_ASZ32_SC1
|
|
d40: LDZX_DSZ64_ASZ32_SC4
|
|
d43: LEA_DSZ64_ASZ32_SC4
|
|
d48: STAD_DSZ64_ASZ32_SC4
|
|
d49: STADTICKLE_DSZ64_ASZ32_SC4
|
|
d4a: LDTICKLE_DSZ64_ASZ32_SC4
|
|
d4b: PORTIN_DSZ64_ASZ16_SC1
|
|
d4f: PORTOUT_DSZ64_ASZ16_SC1
|
|
d50: LDZX_DSZ64_ASZ32_SC4
|
|
d53: LEA_DSZ64_ASZ32_SC4
|
|
d58: STAD_DSZ64_ASZ32_SC4
|
|
d59: STADTICKLE_DSZ64_ASZ32_SC4
|
|
d5a: LDTICKLE_DSZ64_ASZ32_SC4
|
|
d70: LDZX_DSZ64_ASZ32_SC1
|
|
d73: LEA_DSZ64_ASZ32_SC1
|
|
d78: STAD_DSZ64_ASZ32_SC1
|
|
d79: STADTICKLE_DSZ64_ASZ32_SC1
|
|
d7a: LDTICKLE_DSZ64_ASZ32_SC1
|
|
d80: LDZX_DSZ16_ASZ32_SC4
|
|
d83: LEA_DSZ16_ASZ32_SC4
|
|
d88: STAD_DSZ16_ASZ32_SC4
|
|
d89: STADTICKLE_DSZ16_ASZ32_SC4
|
|
d8a: LDTICKLE_DSZ16_ASZ32_SC4
|
|
d8b: PORTIN_DSZ16_ASZ16_SC1
|
|
d8f: PORTOUT_DSZ16_ASZ16_SC1
|
|
d90: LDZX_DSZ16_ASZ32_SC4
|
|
d93: LEA_DSZ16_ASZ32_SC4
|
|
d98: STAD_DSZ16_ASZ32_SC4
|
|
d99: STADTICKLE_DSZ16_ASZ32_SC4
|
|
d9a: LDTICKLE_DSZ16_ASZ32_SC4
|
|
db0: LDZX_DSZ16_ASZ32_SC1
|
|
db3: LEA_DSZ16_ASZ32_SC1
|
|
db8: STAD_DSZ16_ASZ32_SC1
|
|
db9: STADTICKLE_DSZ16_ASZ32_SC1
|
|
dba: LDTICKLE_DSZ16_ASZ32_SC1
|
|
dc0: LDZX_DSZ8_ASZ32_SC4
|
|
dc3: LEA_DSZ8_ASZ32_SC4
|
|
dc8: STAD_DSZ8_ASZ32_SC4
|
|
dc9: STADTICKLE_DSZ8_ASZ32_SC4
|
|
dca: LDTICKLE_DSZ8_ASZ32_SC4
|
|
dcb: PORTIN_DSZ8_ASZ16_SC1
|
|
dcf: PORTOUT_DSZ8_ASZ16_SC1
|
|
dd0: LDZX_DSZ8_ASZ32_SC4
|
|
dd3: LEA_DSZ8_ASZ32_SC4
|
|
dd8: STAD_DSZ8_ASZ32_SC4
|
|
dd9: STADTICKLE_DSZ8_ASZ32_SC4
|
|
dda: LDTICKLE_DSZ8_ASZ32_SC4
|
|
df0: LDZX_DSZ8_ASZ32_SC1
|
|
df3: LEA_DSZ8_ASZ32_SC1
|
|
df8: STAD_DSZ8_ASZ32_SC1
|
|
df9: STADTICKLE_DSZ8_ASZ32_SC1
|
|
dfa: LDTICKLE_DSZ8_ASZ32_SC1
|
|
e00: LDPPHYS_DSZ32_ASZ16_SC1
|
|
e08: STADPPHYS_DSZ32_ASZ16_SC1
|
|
e0a: LDPPHYS_DSZ32_ASZ16_SC1
|
|
e0d: STADPPHYSTICKLE_DSZ32_ASZ16_SC1
|
|
e20: LDPPHYS_DSZ32_ASZ64_SC1
|
|
e25: LDPPHYSTICKLE_DSZ32_ASZ64_SC1
|
|
e28: STADPPHYS_DSZ32_ASZ64_SC1
|
|
e2a: LDPPHYS_DSZ32_ASZ64_SC1
|
|
e2d: STADPPHYSTICKLE_DSZ32_ASZ64_SC1
|
|
e2e: SIMDSTADPPHYS_DSZ32_ASZ64_SC1
|
|
e30: LDPPHYS_DSZ32_ASZ64_SC8
|
|
e38: STADPPHYS_DSZ32_ASZ64_SC8
|
|
e3a: LDPPHYS_DSZ32_ASZ64_SC8
|
|
e40: LDPPHYS_DSZ64_ASZ16_SC1
|
|
e48: STADPPHYS_DSZ64_ASZ16_SC1
|
|
e4a: LDPPHYS_DSZ64_ASZ16_SC1
|
|
e4d: STADPPHYSTICKLE_DSZ64_ASZ16_SC1
|
|
e60: LDPPHYS_DSZ64_ASZ64_SC1
|
|
e65: LDPPHYSTICKLE_DSZ64_ASZ64_SC1
|
|
e68: STADPPHYS_DSZ64_ASZ64_SC1
|
|
e6a: LDPPHYS_DSZ64_ASZ64_SC1
|
|
e6d: STADPPHYSTICKLE_DSZ64_ASZ64_SC1
|
|
e6e: SIMDSTADPPHYS_DSZ64_ASZ64_SC1
|
|
e70: LDPPHYS_DSZ64_ASZ64_SC8
|
|
e75: LDSTGBUF_DSZ64_ASZ16_SC1
|
|
e78: STADPPHYS_DSZ64_ASZ64_SC8
|
|
e7a: LDPPHYS_DSZ64_ASZ64_SC8
|
|
e7d: STADSTGBUF_DSZ64_ASZ16_SC1
|
|
e80: LDPPHYS_DSZ16_ASZ16_SC1
|
|
e88: STADPPHYS_DSZ16_ASZ16_SC1
|
|
e8a: LDPPHYS_DSZ16_ASZ16_SC1
|
|
e8d: STADPPHYSTICKLE_DSZ16_ASZ16_SC1
|
|
ea0: LDPPHYS_DSZ16_ASZ64_SC1
|
|
ea5: LDPPHYSTICKLE_DSZ16_ASZ64_SC1
|
|
ea8: STADPPHYS_DSZ16_ASZ64_SC1
|
|
eaa: LDPPHYS_DSZ16_ASZ64_SC1
|
|
ead: STADPPHYSTICKLE_DSZ16_ASZ64_SC1
|
|
eae: SIMDLSTADSTGBUF_DSZ64_ASZ32_SC1
|
|
eb0: LDPPHYS_DSZ16_ASZ64_SC8
|
|
eb8: STADPPHYS_DSZ16_ASZ64_SC8
|
|
eba: LDPPHYS_DSZ16_ASZ64_SC8
|
|
ec0: LDPPHYS_DSZ8_ASZ16_SC1
|
|
ec8: STADPPHYS_DSZ8_ASZ16_SC1
|
|
eca: LDPPHYS_DSZ8_ASZ16_SC1
|
|
ecb: LDHINT_CACHEALL_ASZ64_SC1
|
|
ecd: STADPPHYSTICKLE_DSZ8_ASZ16_SC1
|
|
edb: LDHINT_CACHE1_ASZ64_SC1
|
|
ee0: LDPPHYS_DSZ8_ASZ64_SC1
|
|
ee5: LDPPHYSTICKLE_DSZ8_ASZ64_SC1
|
|
ee8: STADPPHYS_DSZ8_ASZ64_SC1
|
|
eea: LDPPHYS_DSZ8_ASZ64_SC1
|
|
eeb: LDHINT_CACHE2_ASZ64_SC1
|
|
eed: STADPPHYSTICKLE_DSZ8_ASZ64_SC1
|
|
eee: SIMDHSTADSTGBUF_DSZ64_ASZ32_SC1
|
|
ef0: LDPPHYS_DSZ8_ASZ64_SC8
|
|
ef8: STADPPHYS_DSZ8_ASZ64_SC8
|
|
efa: LDPPHYS_DSZ8_ASZ64_SC8
|
|
f00: LDPPHYS_DSZ32_ASZ32_SC4
|
|
f08: STADPPHYS_DSZ32_ASZ32_SC4
|
|
f0a: LDPPHYS_DSZ32_ASZ32_SC4
|
|
f20: LDPPHYS_DSZ32_ASZ32_SC1
|
|
f28: STADPPHYS_DSZ32_ASZ32_SC1
|
|
f2a: LDPPHYS_DSZ32_ASZ32_SC1
|
|
f30: LDPPHYS_DSZ32_ASZ32_SC8
|
|
f38: STADPPHYS_DSZ32_ASZ32_SC8
|
|
f3a: LDPPHYS_DSZ32_ASZ32_SC8
|
|
f40: LDPPHYS_DSZ64_ASZ32_SC4
|
|
f48: STADPPHYS_DSZ64_ASZ32_SC4
|
|
f4a: LDPPHYS_DSZ64_ASZ32_SC4
|
|
f4b: MPOP
|
|
f4f: MPUSH
|
|
f60: LDPPHYS_DSZ64_ASZ32_SC1
|
|
f65: LDPPHYSTICKLE_DSZ64_ASZ32_SC1
|
|
f68: STADPPHYS_DSZ64_ASZ32_SC1
|
|
f6a: LDPPHYS_DSZ64_ASZ32_SC1
|
|
f6f: MCALL_DIRECT
|
|
f70: LDPPHYS_DSZ64_ASZ32_SC8
|
|
f78: STADPPHYS_DSZ64_ASZ32_SC8
|
|
f7a: LDPPHYS_DSZ64_ASZ32_SC8
|
|
f7f: UCALLPARAM_INDIRECT
|
|
f80: LDPPHYS_DSZ16_ASZ32_SC4
|
|
f88: STADPPHYS_DSZ16_ASZ32_SC4
|
|
f8a: LDPPHYS_DSZ16_ASZ32_SC4
|
|
fa0: LDPPHYS_DSZ16_ASZ32_SC1
|
|
fa8: STADPPHYS_DSZ16_ASZ32_SC1
|
|
faa: LDPPHYS_DSZ16_ASZ32_SC1
|
|
fb0: LDPPHYS_DSZ16_ASZ32_SC8
|
|
fb8: STADPPHYS_DSZ16_ASZ32_SC8
|
|
fba: LDPPHYS_DSZ16_ASZ32_SC8
|
|
fc0: LDPPHYS_DSZ8_ASZ32_SC4
|
|
fc8: STADPPHYS_DSZ8_ASZ32_SC4
|
|
fca: LDPPHYS_DSZ8_ASZ32_SC4
|
|
fe0: LDPPHYS_DSZ8_ASZ32_SC1
|
|
fe8: STADPPHYS_DSZ8_ASZ32_SC1
|
|
fea: LDPPHYS_DSZ8_ASZ32_SC1
|
|
fef: LBSYNC
|
|
ff0: LDPPHYS_DSZ8_ASZ32_SC8
|
|
ff8: STADPPHYS_DSZ8_ASZ32_SC8
|
|
ffa: LDPPHYS_DSZ8_ASZ32_SC8
|
|
fff: SFENCE
|