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Fixes, simplification to LED driver code
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panel_LEDs.vhd
222
panel_LEDs.vhd
@ -53,7 +53,7 @@ use work.Gates_package.EvenParity;
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entity panel_LEDs is
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Generic (
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Clock_divider : integer := 2; -- Default for 50MHz clock is 25MHz = 40ns = 20ns + 20ns
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Clock_divider : integer := 25; -- Default for 50MHz clock is 2, for 25MHz = 40ns = 20ns + 20ns. 25 gives 2MHz.
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Number_LEDs : integer := 256
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);
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Port ( -- Lamp input vector
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@ -63,10 +63,7 @@ entity panel_LEDs is
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-- Driver outputs
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MAX7219_CLK : out std_logic;
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MAX7219_DIN0 : out std_logic; -- LEDs 00-3F
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MAX7219_DIN1 : out std_logic; -- LEDs 40-7F
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MAX7219_DIN2 : out std_logic; -- LEDs 80-BF
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MAX7219_DIN3 : out std_logic; -- LEDs C0-FF
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MAX7219_DIN : out std_logic; -- LEDs 00-3F
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MAX7219_LOAD : out std_logic; -- Data latched on rising edge
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MAX6951_CLK : out std_logic;
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@ -80,78 +77,86 @@ end panel_LEDs;
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architecture Behavioral of panel_LEDs is
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signal clk_out : std_logic := '0';
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signal shift_reg64 : std_logic_vector(63 downto 0);
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signal reg_counter : integer range 0 to 11 := 0;
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signal bit_counter16 : integer range 0 to 16 := 0;
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signal bit_counter64 : integer range 0 to 64 := 0;
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-- MAX7219 data is 8b address and 8b data
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-- Address is:
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-- 00 No-op (unused)
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-- 01 Digit 0 (in position 0)
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-- ...
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-- 08 Digit 7 (in position 0)
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-- 09 Decode mode (fixed at default)
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-- 0A Intensity (fixed at 0F in position 8)
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-- 0B Scan limit (fixed at 07 in position 9)
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-- 0C Shutdown (fixed at 01 in position 10)
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-- 0F Display test (fixed at 00 in position 11)
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-- 08 Digit 7 (in position 7)
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-- 09 Decode mode (fixed 00 in position 8)
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-- 0A Intensity (fixed at 0F in position 9)
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-- 0B Scan limit (fixed at 07 in position 10)
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-- 0C Shutdown (fixed at 01 in position 11)
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-- 0F Display test (fixed at 00 in position 12)
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type registers7219 is array(0 to 3,0 to 11) of std_logic_vector(15 downto 0);
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type registers7219 is array(0 to 3,0 to 12) of std_logic_vector(15 downto 0);
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signal max7219_vector : registers7219 :=
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(
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0 => (
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0 => "0000000000000000",
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1 => "0000000100000000",
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2 => "0000001000000000",
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3 => "0000001100000000",
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4 => "0000010000000000",
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5 => "0000010100000000",
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6 => "0000011000000000",
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7 => "0000011100000000",
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8 => "0000101000000000",
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9 => "0000101100000111",
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10 => "0000110000000001",
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11 => "0000111100000000"
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0 => "0000000100000000",
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1 => "0000001000000000",
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2 => "0000001100000000",
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3 => "0000010000000000",
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4 => "0000010100000000",
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5 => "0000011000000000",
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6 => "0000011100000000",
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7 => "0000100000000000",
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8 => "0000100100000000",
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9 => "0000101000001111",
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10 => "0000101100000111",
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11 => "0000110000000001",
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12 => "0000111100000000"
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),
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1 => (
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0 => "0000000000000000",
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1 => "0000000100000000",
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2 => "0000001000000000",
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3 => "0000001100000000",
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4 => "0000010000000000",
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5 => "0000010100000000",
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6 => "0000011000000000",
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7 => "0000011100000000",
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8 => "0000101000000000",
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9 => "0000101100000111",
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10 => "0000110000000001",
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11 => "0000111100000000"
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0 => "0000000100000000",
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1 => "0000001000000000",
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2 => "0000001100000000",
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3 => "0000010000000000",
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4 => "0000010100000000",
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5 => "0000011000000000",
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6 => "0000011100000000",
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7 => "0000100000000000",
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8 => "0000100100000000",
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9 => "0000101000001111",
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10 => "0000101100000111",
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11 => "0000110000000001",
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12 => "0000111100000000"
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),
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2 => (
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0 => "0000000000000000",
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1 => "0000000100000000",
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2 => "0000001000000000",
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3 => "0000001100000000",
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4 => "0000010000000000",
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5 => "0000010100000000",
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6 => "0000011000000000",
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7 => "0000011100000000",
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8 => "0000101000000000",
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9 => "0000101100000111",
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10 => "0000110000000001",
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11 => "0000111100000000"
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0 => "0000000100000000",
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1 => "0000001000000000",
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2 => "0000001100000000",
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3 => "0000010000000000",
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4 => "0000010100000000",
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5 => "0000011000000000",
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6 => "0000011100000000",
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7 => "0000100000000000",
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8 => "0000100100000000",
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9 => "0000101000001111",
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10 => "0000101100000111",
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11 => "0000110000000001",
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12 => "0000111100000000"
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),
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3 => (
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0 => "0000000000000000",
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1 => "0000000100000000",
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2 => "0000001000000000",
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3 => "0000001100000000",
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4 => "0000010000000000",
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5 => "0000010100000000",
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6 => "0000011000000000",
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7 => "0000011100000000",
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8 => "0000101000000000",
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9 => "0000101100000111",
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10 => "0000110000000001",
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11 => "0000111100000000"
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0 => "0000000100000000",
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1 => "0000001000000000",
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2 => "0000001100000000",
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3 => "0000010000000000",
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4 => "0000010100000000",
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5 => "0000011000000000",
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6 => "0000011100000000",
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7 => "0000100000000000",
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8 => "0000100100000000",
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9 => "0000101000001111",
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10 => "0000101100000111",
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11 => "0000110000000001",
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12 => "0000111100000000"
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)
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);
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@ -179,7 +184,7 @@ signal max6951_vector : registers6951 :=
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5 => "0110010100000000",
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6 => "0110011000000000",
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7 => "0110011100000000",
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8 => "0000001000000000",
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8 => "0000001000001111",
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9 => "0000001100000111",
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10 => "0000010000000001",
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11 => "0000011100000000"
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@ -194,7 +199,7 @@ signal max6951_vector : registers6951 :=
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5 => "0110010100000000",
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6 => "0110011000000000",
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7 => "0110011100000000",
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8 => "0000001000000000",
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8 => "0000001000001111",
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9 => "0000001100000111",
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10 => "0000010000000001",
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11 => "0000011100000000"
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@ -208,7 +213,7 @@ signal max6951_vector : registers6951 :=
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5 => "0110010100000000",
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6 => "0110011000000000",
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7 => "0110011100000000",
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8 => "0000001000000000",
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8 => "0000001000001111",
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9 => "0000001100000111",
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10 => "0000010000000001",
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11 => "0000011100000000"
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@ -222,7 +227,7 @@ signal max6951_vector : registers6951 :=
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5 => "0110010100000000",
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6 => "0110011000000000",
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7 => "0110011100000000",
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8 => "0000001000000000",
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8 => "0000001000001111",
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9 => "0000001100000111",
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10 => "0000010000000001",
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11 => "0000011100000000"
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@ -244,83 +249,76 @@ gen_clk : process (clk) is
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end if;
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end process;
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max7219 : process (clk_out) is
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variable reg_counter : integer := 0;
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variable bit_counter : integer := 16;
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variable shift_reg0,shift_reg1,shift_reg2,shift_reg3 : std_logic_vector(16 downto 0);
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begin
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if falling_edge(clk_out) then
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if bit_counter=0 then
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bit_counter := 16;
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if reg_counter=9 then
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reg_counter := 0;
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else
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if reg_counter=9 then
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reg_counter := 0;
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else
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reg_counter := reg_counter + 1;
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end if;
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if bit_counter64=0 then
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bit_counter64 <= 64;
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case reg_counter is
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when 0 to 7 =>
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shift_reg0 := '0' & max7219_vector(0,reg_counter)(15 downto 8) & LEDs(reg_counter*8+0 to reg_counter*8+7);
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shift_reg1 := '0' & max7219_vector(1,reg_counter)(15 downto 8) & LEDs(reg_counter*8+64 to reg_counter*8+71);
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shift_reg2 := '0' & max7219_vector(2,reg_counter)(15 downto 8) & LEDs(reg_counter*8+128 to reg_counter*8+135);
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shift_reg3 := '0' & max7219_vector(3,reg_counter)(15 downto 8) & LEDs(reg_counter*8+192 to reg_counter*8+199);
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-- Mapping is:
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-- b7 = DP = XX7
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-- b6 = A = XX0
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-- b5 = B = XX1
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-- b4 = C = XX2
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-- b3 = D = XX3
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-- b2 = E = XX4
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-- b1 = F = XX5
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-- b0 = G = XX6
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shift_reg64 <=
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max7219_vector(3,reg_counter)(15 downto 8) & LEDs(reg_counter*8+192+7) & LEDs(reg_counter*8+192 to reg_counter*8+192+6) &
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max7219_vector(2,reg_counter)(15 downto 8) & LEDs(reg_counter*8+128+7) & LEDs(reg_counter*8+128 to reg_counter*8+128+6) &
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max7219_vector(1,reg_counter)(15 downto 8) & LEDs(reg_counter*8+ 64+7) & LEDs(reg_counter*8+ 64 to reg_counter*8+ 64+6) &
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max7219_vector(0,reg_counter)(15 downto 8) & LEDs(reg_counter*8+ 0+7) & LEDs(reg_counter*8+ 0 to reg_counter*8+ 0+6);
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when others =>
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shift_reg0 := '0' & max7219_vector(0,reg_counter);
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shift_reg1 := '0' & max7219_vector(1,reg_counter);
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shift_reg2 := '0' & max7219_vector(2,reg_counter);
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shift_reg3 := '0' & max7219_vector(3,reg_counter);
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shift_reg64 <=
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max7219_vector(3,reg_counter) &
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max7219_vector(2,reg_counter) &
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max7219_vector(1,reg_counter) &
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max7219_vector(0,reg_counter);
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end case;
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end if;
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if reg_counter=12 then
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reg_counter <= 0;
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else
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bit_counter := bit_counter - 1;
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shift_reg0 := shift_reg0(15 downto 0) & '0';
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shift_reg1 := shift_reg1(15 downto 0) & '0';
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shift_reg2 := shift_reg2(15 downto 0) & '0';
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shift_reg3 := shift_reg3(15 downto 0) & '0';
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reg_counter <= reg_counter + 1;
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end if;
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if bit_counter=16 then
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MAX7219_LOAD <= '1';
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MAX7219_DIN <= '0';
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MAX7219_Load <= '1';
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else
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MAX7219_LOAD <= '0';
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bit_counter64 <= bit_counter64 - 1;
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shift_reg64 <= shift_reg64(62 downto 0) & '0';
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MAX7219_DIN <= shift_reg64(63);
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MAX7219_Load <= '0';
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end if;
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MAX7219_DIN0 <= shift_reg0(16);
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MAX7219_DIN1 <= shift_reg1(16);
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MAX7219_DIN2 <= shift_reg2(16);
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MAX7219_DIN3 <= shift_reg3(16);
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end if;
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end process;
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max6951 : process (clk_out) is
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variable dev_counter : integer := 3;
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variable reg_counter : integer := 0;
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variable bit_counter : integer := 16;
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variable dev_counter : integer range 0 to 3 := 3;
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variable reg_counter : integer range 0 to 11 := 0;
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variable bit_counter : integer range 0 to 16 := 16;
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variable shift_reg : std_logic_vector(16 downto 0);
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begin
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if falling_edge(clk_out) then
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if bit_counter=0 then
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bit_counter := 16;
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if reg_counter=9 then
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case reg_counter is
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when 0 to 7 =>
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shift_reg := '0' & max6951_vector(dev_counter,reg_counter)(15 downto 8) & LEDs(dev_counter*64+reg_counter*8 to dev_counter*64+reg_counter*8+7);
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when others =>
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shift_reg := '0' & max6951_vector(dev_counter,reg_counter);
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end case;
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if reg_counter=11 then
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if dev_counter=0 then
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dev_counter := 3;
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else
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dev_counter := dev_counter - 1;
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end if;
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reg_counter := 0;
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else
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if reg_counter=9 then
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reg_counter := 0;
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else
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reg_counter := reg_counter + 1;
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end if;
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case reg_counter is
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when 0 to 7 =>
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shift_reg := '0' & max6951_vector(dev_counter,reg_counter)(15 downto 8) & LEDs(dev_counter*64+reg_counter*8 to dev_counter*64+reg_counter*8+7);
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when others =>
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shift_reg := '0' & max6951_vector(dev_counter,reg_counter);
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end case;
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end if;
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else
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bit_counter := bit_counter - 1;
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shift_reg := shift_reg(15 downto 0) & '0';
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